Voltage controlled sub-THz detection with gated planar asymmetric nanochannels

[EN]This letter reports on room temperature sub-THz detection using self-switching diodes based on an AlGaN/GaN heterostructure on a Si substrate. By means of free-space measurements at 300 GHz, we demonstrate that the responsivity and noise equivalent power (NEP) of sub-THz detectors based on planar asymmetric nanochannels can be improved and voltage controlled by means of a top gate electrode. A simple quasi-static model based on the DC measurements of the current-voltage curves is able to predict the role of the gate bias in its performance. The best values of voltage responsivity and NEP are achieved when the gate bias approaches the threshold voltage, around 600 V/W and 50 pW/Hz1/2, respectively. A good agreement is found between modeled results and those obtained from RF measurements under probes at low frequency (900MHz) and in free-space at 300 GHz

Design of circuits for sub-threshold voltages : implementation of adders

The demand and the need for low-power circuits is an ever increasing trend particularly due to the added overhead of design of efficient cooling systems or more sophisticated and expensive packaging techniques. In most new emerging applications that demand low power consumption such as biomedical implants, wearable devices, micro-sensor nodes and countless others, energy efficiency emphasis far supersedes the traditional focus on improving the speed. Such energy constrained systems can be operated at considerably reduced performance levels in order to save power and extend their battery lifetimes. Sub-Threshold design has proven useful for ultra-low power and low energy applications since the dynamic power is reduced quadratically with supply voltage; the least energy operation usually takes place in the sub-threshold region. This work provides a comprehensive analysis of the CMOS standard cell characterization in the sub-threshold region, layout, logical library extraction, optimization and top-level implementation of 2 of the parallel prefix adders of different word sizes in 45nm technology with comparison between the sub-threshold region and strong inversion regions of operation. The analysis is done on PPA: power (energy), performance and area, the common metrics for any chip design. The switching activities of the circuits were captured using dynamic gate level simulation to perform the time based peak power analysis. Static timing analysis was performed to estimate the delay of the critical path for each circuit. The analysis and results presented in this report will be helpful in choosing a specific adder configuration for an integrated circuit based on the constraints related to its application.Electrical and Computer Engineerin

Design and performance analysis of Tri-gate GaN HEMTs

GaN-based high electron mobility transistors (HEMT) are promising devices for radio frequency (RF) and high-power electronics and are already in use for RF power amplifiers and for power switches. Commonly, these devices are normally-on transistors, i.e., they are in the on-state at zero applied gate voltage, what limits their suitability for various applications, such as fail-safe power switches and RF amplifiers with single-polarity power supply. Unfortunately, in contrast to GaAs- and InP HEMTs, achieving normally-off operation, i.e., a positive thresh-old voltage, for GaN heterostructures is difficult due to the high density of the polarization-induced two-dimensional electron gas (2DEG) at the barrier/buffer interface. For fast RF HEMTs, short gates are required. However, HEMTs with aggres-sively scaled gate length frequently suffer from short-channel effects caused by a degraded control of the gate over the channel. This leads to a deterioration of the transistors off-state performance (increased subthreshold swing and drain-induced barrier lowering) and on-state behavior (increased drain conductance). The tri-gate design has recently been applied to MOSFETs and HEMTs to improve the gate control and suppress short channel effects. Experimental tri-gate transistors show excellent down-scaling characteristics, improved performance, and, in particular for GaN tri-gate HEMTs, a significant shift of the threshold voltage toward positive values. On the other hand, tri-gate GaN normally-off HEMTs are still suffering from increased parasitics causing degraded RF performance (particularly in terms of cutoff frequency) compared to their planar counterparts. Improving the RF performance of GaN tri-gate HEMTs by reducing the parasitics is essential, but this requires a deep understanding of device physics and a thorough analysis of the root causes. In the present work, in-depth theoretical investigations of GaN tri-gate HEMT operation are performed and extensive simulation studies for these devices are conducted. As a result of these efforts, improved insights in the physics of GaN tri-gate HEMTs are achieved, the potential of this transistor type is assessed, design guidelines are elaborated, and advantageous designs are developed. It is shown that the 2DEG sheet density decreases by shrinking the body width, that the threshold voltage of GaN tri-gate HEMTs strongly depends on the width of AlGaN/GaN bodies, and that solely by decreasing the body width a transition from normally-on to normally-off operation can be achieved. The separation between adjacent bodies is shown to have less impact on threshold voltage. The results also show that for wide bodies (> 200 nm) the channel is controlled by both the top-gate and the sidewall gates, while for decreasing body width the control by top-gate gradually diminishes and the channel will be only controlled by side-gates. Furthermore, the impact of AlGaN barrier design (Al content, thickness) is studied, and the results show a limited dependency of the threshold voltage on the barrier design for very narrow bodies. The tri-gate concept enables normally-off operation, provides improved on-state performance (higher transconductance), and effectively suppresses short-channel effects in the off-state. Moreover, the simulation results show that GaN tri-gate HEMTs can exhibit higher breakdown voltages and operate closer to the theoretical limit for GaN devices than their planar counterparts. Moreover, the simulations indicate that the RF performance of GaN tri-gate HEMTs with optimized body designs can be superior to that of conventional planar devices. A means to improve the RF performance is the reduction of the body etch height, leading to a decreased parasitic coupling between the sidewalls and the source/drain electrodes. Thus, reducing the body height leads to a decreased overall gate capacitance and an improved RF performance. Another way to reduce the overall gate capacitance is to cover the body sidewalls with a dielectric (e.g. SiN). This reduces the fringing capacitance components since the gap between neighboring bodies that is filled with gate metal is narrower compared to the case without dielectrics. Finally, the polarization charge at the barrier/channel interface and thus the electron density in the 2DEG) can be increased either by increasing the aluminium content of the AlGaN barrier or by using a different barrier material (e.g., lattice matched In0.17 Al0.83 N). In the frame of a joint DFG project, GaN tri-gate HEMTs designed based on the improved insights in the physics of these devices have been fabricated and characterized at Fraunhofer IAF. These devices having a gate length of 100 nm are by far the fastest GaN tri-gate HEMTs worldwide and show record performance in terms of cutoff frequency (120 GHz) and maximum frequency of oscillation (300 GHz).HEMTs (high electron mobility transistors) auf GaN-Basis besitzen großes Potenzial für die HF- (Hochfrequenz) und Leistungselektronik und werden bereits in HF-Leistungsverstärkern und als Leistungsschalter verwendet. Üblicherweise sind GaN HEMTs Normally-On Transistoren (d.h. Transistoren, die sich bei einer Gatespannung von 0 V im Ein-Zustand befinden), was für Anwendungen wie Fail-Safe-Leistungsschalter und HF-Verstärker mit nur einer Versorgungsspannung nachteilig ist. Es schwierig, GaN HEMTs mit Normally-Off-Charakteristik (HEMTs mit positiver Schwellspannung) zu realisieren, da in diesen Transistoren die Dichte des sich an der Grenzfläche Barriere/Puffer ausbildenden 2DEG (zweidimensionales Elektronengas) auf Grund starker Polarisationseffekte erheblich größer als in GaAs und InP HEMTs ist. Die Realisierung schneller HF-HEMTs erfordert kurze Gates. Allerdings leiden Transistoren mit sehr kurzen Gates häufig unter Kurzkanaleffekten und einer reduzierten Steuerwirkung des Gates, was zu einer Verschlechterung des Verhaltens im Aus-Zustand (erhöhte Werte für den Subthreshold Swing und das Drain-Induced Barrier Low-ering) und im Ein-Zustand (erhöhter Drainleitwert) führt. In jüngster Zeit wird bei MOSFETs und HEMTs das Tri-Gate-Design angewendet, um die Gatesteuerwirkung zu verbessern und Kurzkanaleffekte zu unterdrücken. So wurden bereits Tri-Gate-Transistoren mit ausgezeichnetem Skalierungsverhalten, verbesserten Eigenschaften und, speziell im Fall von GaN Tri-Gate-HEMTs, positiver Schwellspannung, demonstriert. Auf der anderen Seite leiden GaN Tri-Gate-HEMTs mit Normally-Off-Charakteristik jedoch unter großen Parasitäten, die das HF-Verhalten (insbesondere die Transitfrequenz) beeinträchtigen. Die Verbesserung des HF-Verhaltens und eine Reduzierung der Parasitäten von GaN Tri-Gate-HEMTs ist daher dringend nötig. Das erfordert jedoch ein tiefes Eindringen in die Physik dieser Bauelemente. In der vorliegenden Arbeit werden umfassende theoretische Untersuchungen und Bauelementesimulationen zu GaN Tri-Gate-HEMT beschrieben, die zu einem deutlichen verbesserten Verständnis der Wirkungsweise von GaN Tri-Gate-HEMTs führten. So konnten das Potential dieses Transistortyps bewertet, Designregeln erarbeitet und vorteilhafte Transistordesigns entwickelt werden. In der Arbeit wird gezeigt, dass eine Verringerung der Bodyweite bei gegebener Gatespannung zu einer Verringerung der Ladungsträgerdichte im 2DEG führt, dass die Schwellspannung maßgeblich von der Bodyweite bestimmt wird und dass bei hinreichend geringer Bodyweite der Übergang vom Normall-On- zum Normally-Off-Betrieb erfolgt. Es wird auch gezeigt, dass der Abstand zwischen benachbarten Bodies nur einen geringen Einfluss auf die Schwellspannung hat. Darüber hinaus wird demonstriert, dass im Fall weiter Bodies (> 200 nm) der Kanal sowohl durch das Top-Gate als auch durch die Seiten-Gates gesteuert wird, während bei schmaleren Bodies die Steuerwirkung durch das Top-Gate geringer wird und die Verhältnisse im Kanal im Wesentlichen durch das Seiten-Gates bestimmt werden. In der Arbeit wird weiterhin Rolle des Designs der AlGaN-Barriere (Al-Gehalt, Dicke) untersucht und demonstriert, dass die Gestaltung der Barriere bei schmalen Bodies nur einen begrenzten Einfluss auf die Schwellspannung hat. Die Untersuchungen zeigen deutlich, dass das mit dem Tri-Gate-Konzept Normally-Off-Transistoren realisierbar sind, dass das Transistorverhalten im Ein-Zustand verbessert (höhere Steilheit) wird, und dass Kurzkanaleffekte im Aus-Zustand wirkungsvoll unterdrückt. Es wird auch demonstriert, dass GaN Tri-Gate HEMTs höhere Durchbruchspannungen zeigen und näher an der theoretischen Grenze für GaN-Bauelemente arbeiten als planare GaN HEMTs. Ein weiteres Ergebnis der vorliegenden Arbeit ist der Nachweis, dass GaN Tri-Gate-HEMTs mit sorgfältig optimiertem Design den planaren HEMTs auch hinsichtlich des HF-Verhaltens überlegen sind. Ein Mittel zur Verbesserung des HF-Verhaltens ist die Reduzierung der Body-Ätzhöhe, die zur Verringerung der parasitären Kopplung zwischen den Body-Seitenwänden und den Source/Drain-Elektroden und somit zu einer geringeren Gatekapazität führt. Eine weitere Maßnahme zur Reduzierung der Gatekapazität ist die Beschichtung der Body-Seitenwände mit einem Dielektrikum (z.B. SiN). Das verringert die Streukapazität, da jetzt die mit dem Gatemetall gefüllte Lücken zwischen benachbarten Bodies schmaler sind. Schließlich wird gezeigt, dass die Polarisationsladung an der Grenzfläche Barrier/Kanal und somit die Elektronendichte im 2DEG durch Erhöhung des Al-Gehalts der AlGaN-Barriere oder durch Nutzung eines anderen Materials für die Barriere (z.B. gitterangepasstes In0.17 Al0.83 N) gesteigert werden kann

Multi-port Memory Design for Advanced Computer Architectures

In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters. Multi-porting is essential for caches and shared-data systems, especially multi-core System-on-chips (SOC). It can significantly increase the memory access throughput. We evaluate FinFET voltage-mode multi-port SRAM cells using different metrics including leakage current, static noise margin and read/write performance. Simulation results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over classical double-ended structures at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended multi-port structures can achieve equivalent write performance to the classical double-ended multi-port structure for 9% area overhead. Moreover, compared with CMOS SRAM, FinFET SRAM has better stability and standby power. We also describe new methods for the design of FinFET current-mode multi-port SRAM cells. Current-mode SRAMs avoid the full-swing of the bitline, reducing dynamic power and access time. However, that comes at the cost of voltage drop, which compromises stability. The design proposed in this thesis utilizes the feature of Independent Gate (IG) mode FinFET, which can leverage threshold voltage by controlling the back gate voltage, to merge two transistors into one through high-Vt and low-Vt transistors. This design not only reduces the voltage drop, but it also reduces the area in multi-port current-mode SRAM design. For off-chip memory, we propose a novel two-port 1-read, 1-write (1R1W) phasechange memory (PCM) cell, which significantly reduces the probability of blocking at the bank levels. Different from the traditional PCM cell, the access transistors are at the top and connected to the bitline. We use Verilog-A to model the behavior of Ge2Sb2Te5 (GST: the storage component). We evaluate the performance of the two-port cell by transistor sizing and voltage pumping. Simulation results show that pMOS transistor is more practical than nMOS transistor as the access device when both area and power are considered. The estimated area overhead is 1.7�, compared to single-port PCM cell. In brief, the contribution we make in this thesis is that we propose and evaluate three different kinds of multi-port memories that are favorable for advanced computer architectures

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon Wnanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V-T). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V-T. This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of similar to 0.5 V between low-V-T and high-V-T configurations, while high-V-T configuration reduces the leakage current by two orders of magnitude as compared to low-V-T configuration

GaAs optoelectronic neuron arrays

A simple optoelectronic circuit integrated monolithically in GaAs to implement sigmoidal neuron responses is presented. The circuit integrates a light-emitting diode with one or two transistors and one or two photodetectors. The design considerations for building arrays with densities of up to 10^4 cm^-2 are discussed

Nanowire Zinc Oxide MOSFET Pressure Sensor

Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology