CoBe -- Coded Beacons for Localization, Object Tracking, and SLAM Augmentation

This paper presents a novel beacon light coding protocol, which enables fast and accurate identification of the beacons in an image. The protocol is provably robust to a predefined set of detection and decoding errors, and does not require any synchronization between the beacons themselves and the optical sensor. A detailed guide is then given for developing an optical tracking and localization system, which is based on the suggested protocol and readily available hardware. Such a system operates either as a standalone system for recovering the six degrees of freedom of fast moving objects, or integrated with existing SLAM pipelines providing them with error-free and easily identifiable landmarks. Based on this guide, we implemented a low-cost positional tracking system which can run in real-time on an IoT board. We evaluate our system's accuracy and compare it to other popular methods which utilize the same optical hardware, in experiments where the ground truth is known. A companion video containing multiple real-world experiments demonstrates the accuracy, speed, and applicability of the proposed system in a wide range of environments and real-world tasks. Open source code is provided to encourage further development of low-cost localization systems integrating the suggested technology at its navigation core

RADIX-10 PARALLEL DECIMAL MULTIPLIER

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters

Fast decimal floating-point division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literatureHooman Nikmehr, Braden Phillips and Cheng-Chew Li

Study on a Compact and High Speed 4-bit BCD Adder

Speed, simplicity and efficiency in data storage are the highlights of using binary data for arithmetic operations in computer systems. But it is an irony that human beings have preferred decimal as the number base for all calculations done by hand even with the advent of binary data. Commercial databases contain more decimal data and their consequent conversion to binary and then back to decimal when used with binary arithmetic hardware reiterates the need for a decimal arithmetic hardware support in financial and commercial applications. As the use of an adder circuit is indispensable in both platforms of binary and decimal we opt the Binary Coded Decimal (BCD) adder. Compactness of gadgets, speed and abating power consumption has turned out to be an inevitable aspect over a plethora of applications. Concentrating on reducing area here we analyze different 1-bit adder cells namely SERF adder, 10T adder, 8T adder, and 6T adder cells. Simulations were done in Cadence Virtuoso tool at 180nm and 90nm for technology independence. The 6T adder outperforms in terms of area, power and PDP and is implemented in 4-bit BCD adder estimating the delay and power consumed against the conventional design in 90nm technology. Simulation results estimate that the proposed BCD adder outperforms the conventional design in all design aspects of area, power, PDP and delay

Design, implementation & first run problems of a factory corporate network

En aquest projecte s'ha dut a terme el disseny de la infraestructura de comunicacions i de xarxa d'una fàbrica que comptarà amb zones de producció i d’oficines corporatives, s'han analitzat les subseqüents necessitats dels recursos de comunicacions dels diferents departaments per determinar els equipaments de xarxa necessaris, així com la topologia de la jerarquia d'interconnexions. Igualment, s'ha tingut en compte la infraestructura de connexions sense fils per donar cobertura als dispositius tant corporatius com de dispositius personals o treballadors externs. Un cop establerta la topologia de xarxa, s'ha realitzat l'assignació d'adreces IP, segmentant la xarxa en diferents VLANs segons una classificació de funcionalitats i necessitats de la mateixa (nombre de dispositius, servidor DHCP, nivells de seguretat…) Finalment, s'ha realitzat un estudi econòmic respecte al pressupost del qual es disponia per al projecte i el que finalment ha fet falta per cobrir tot el material, obres i hores d’enginyeria necessaris per a la realització d'aquest.In this project, the design of the communications and network infrastructure of a factory that will have production areas and corporate offices has been carried out, the subsequent needs of the communications resources of the different departments have been analyzed for determine the necessary network equipment, as well as the topology of the interconnection hierarchy. Similarly, the infrastructure of wireless connections has been taken into account to provide coverage for both corporate devices and personal devices or external workers. Once the network topology has been established, the assignment of IP addresses has been carried out, segmenting the network into different VLANs according to a classification of functionalities and its needs (number of devices, DHCP server, security levels...) Finally , an economic study has been carried out with respect to the budget that was available for the project and what was ultimately needed to cover all the material, works and hours of engineering necessary to carry it out

MIDAS, prototype Multivariate Interactive Digital Analysis System, Phase 1. Volume 2: Diagnostic system

The MIDAS System is a third-generation, fast, multispectral recognition system able to keep pace with the large quantity and high rates of data acquisition from present and projected sensors. A principal objective of the MIDAS Program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughout. The hardware and software generated in Phase I of the over-all program are described. The system contains a mini-computer to control the various high-speed processing elements in the data path and a classifier which implements an all-digital prototype multivariate-Gaussian maximum likelihood decision algorithm operating 2 x 105 pixels/sec. Sufficient hardware was developed to perform signature extraction from computer-compatible tapes, compute classifier coefficients, control the classifier operation, and diagnose operation. Diagnostic programs used to test MIDAS' operations are presented

Semantic multimedia remote display for mobile thin clients

Current remote display technologies for mobile thin clients convert practically all types of graphical content into sequences of images rendered by the client. Consequently, important information concerning the content semantics is lost. The present paper goes beyond this bottleneck by developing a semantic multimedia remote display. The principle consists of representing the graphical content as a real-time interactive multimedia scene graph. The underlying architecture features novel components for scene-graph creation and management, as well as for user interactivity handling. The experimental setup considers the Linux X windows system and BiFS/LASeR multimedia scene technologies on the server and client sides, respectively. The implemented solution was benchmarked against currently deployed solutions (VNC and Microsoft-RDP), by considering text editing and WWW browsing applications. The quantitative assessments demonstrate: (1) visual quality expressed by seven objective metrics, e.g., PSNR values between 30 and 42 dB or SSIM values larger than 0.9999; (2) downlink bandwidth gain factors ranging from 2 to 60; (3) real-time user event management expressed by network round-trip time reduction by factors of 4-6 and by uplink bandwidth gain factors from 3 to 10; (4) feasible CPU activity, larger than in the RDP case but reduced by a factor of 1.5 with respect to the VNC-HEXTILE

Developing the ZigBee Based Data Payload Coding for Data Communication in Microgrids

A data coding is presented in this paper for ZigBee-based wireless data communication system for future microgrids. It is assumed that each microgrid has a central controller and each distributed generation unit in the microgrid has a local controller. The communication system is responsible for transmitting and receiving data amongst these controllers. This communication system is based on ZigBee technology, which has low cost and low power consumption. The required data to be transferred are defined and a suitable coding is also proposed. Finally, the number of transmitted symbols and the processing time delay of the proposed data coding are numerically analyzed

Development and testing of laser Doppler system components for wake vortex monitoring. Volume 2: Scanner operations manual

The theory and operation of the scanner portion of the laser Doppler system for detecting and monitoring aircraft trailing vortices in an airport environment are discussed. Schematics, wiring diagrams, component values, and operation and checkout procedures are included