Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

Design for testability of high-order OTA-C filters

Copyright © 2016 John Wiley & Sons, Ltd.A study of oscillation-based test for high-order Operational Transconductance Amplifier-C (OTA-C) filters is presented. The method is based on partition of a high-order filter into second-order filter functions. The opening Q-loop and adding positive feedback techniques are developed to convert the second-order filter section into a quadrature oscillator. These techniques are based on an open-loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth-order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth-order cascade, inverse follow-the-leader feedback (IFLF) and LF OTA-C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation-based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA-C filters, respectively. Copyright ÂPeer reviewe

Oscillation-Based Test Structure and Method for OTA-C Filters

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a design for testability technique for operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. The oscillation frequency may be considered as a digital signal and it can be evaluated using digital circuitry therefore the test time is very small. These characteristics imply that the proposed method is very suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of two integrator loop and Tow-Thomas filters. Simulation results in 0.25 mum CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters has 87% fault coverage and with a minimum number of extra components, requires a negligible area overhead

A performance evaluation of oscillation based test in continuous time filters

This work evaluates the ability of OBT for detecting parametric faults in continuous-time filters. To this end, we adopt two filters with quite different topologies as cases of study and a previously reported statistical fault model. In addition, we explore the behavior of the test schemes when a particular test condition is changed. The new data reported here, obtained from a fault simulation process, reveal a lower performance of OBT not observed in previous work using single-deviation faults, even under the change in the test condition.publishedVersionFil: Romero, Eduardo Abel. Universidad Tecnológica Nacional. Facultad Regional Villa María; Argentina.Fil: Romero, Eduardo Abel. Universidad Nacional de Córdoba. Facultad de Matemática, Astronomía y Física; Argentina.Fil: Costamagna, Marcelo. Universidad Tecnológica Nacional. Facultad Regional Villa María; Argentina.Fil: Peretti, Gabriela Marta. Universidad Tecnológica Nacional. Facultad Regional Villa María; Argentina.Fil: Peretti, Gabriela Marta. Universidad Nacional de Córdoba. Facultad de Matemática, Astronomía y Física; Argentina.Fil: Marqués, Carlos Alberto. Universidad Nacional de Córdoba. Facultad de Matemática, Astronomía y Física; Argentina.Otras Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Informació

Low-cost dc bist for analog circuits: a case study

This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.Fil: Petrashin, Pablo. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Carrera de Ingeniería Electrónica; Argentina.Fil: Dualibe, Carlos. Universidad Católica de Córdoba. Facultad de Ingeniería. Laboratorio de Microelectrónica; Argentina.Fil: Lancioni, Walter. Universidad Cátólica de Córdoba. Facultad de Ingeniería; Argentina.Fil: Toledo, Luis. Universidad Católica de Córdoba; Argentina.Otras Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Informació

Various Order Low–Pass Filter with the Electronic Change of Its Approximation

A design of a low pass frequency filter with the electronic change of the approximation characteristics of resulting responses is presented. The filter also offers the reconnection–less reconfiguration of the order (1st, 2nd, 3rd and 4th order functions are available). Furthermore, the filter offers the electronic control of the cut–off frequency of the output response. The feature of the electronic change of the approximation characteristics has been investigated for Butterworth, Bessel, Cauer, Chebyshev and Inverse Chebyshev approximations. The design is verified by PSpice simulations and experimental measurements. The results are also supported by the transient domain response (response to the square waveform), comparison of group delay, sensitivity analysis and implementation feasibility based on given approximation. The benefit of the proposed electronic change of the approximation characteristics feature (in general signal processing or for sensors in particular) has been presented and discussed for an exemplary scenario

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Abbreviations and acronyms

This booklet provides a partial list of acronyms, abbreviations, and other short word forms, including their definitions, used in documents at the Goddard Space Flight Center (GSFC). This list does not preclude the use of other short forms of less general usage, as long as these short forms are identified the first time they appear in a document and are defined in a glossary in the document in which they are used. This document supplements information in the GSFC Scientific and Technical Information Handbook (GHB 2200.2/April 1989). It is not intended to contain all short word forms used in GSFC documents; however, it was compiled of actual short forms used in recent GSFC documents. The entries are listed first, alphabetically by the short form, and then again alphabetically by definition

Influence of PVT variation and threshold selection on OBT and OBIST fault detection in RFCMOS amplifiers

Please read abstract in the article.The NRF/F.RS.-FNRS South Africa–Wallonia Joint Science and Technology Research Collaboration.https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8784029hj2024Electrical, Electronic and Computer EngineeringSDG-09: Industry, innovation and infrastructur

Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications