An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Low-Density-Parity-Check (LDPC) based error control decoders find wide range of application in both storage and communication systems, because of the merits they possess which include high appropriateness towards parallelization and excellent performance in error correction. Field-Programmable Gate Array (FPGA) has provided a robust platform in terms of parallelism, resource allocation and excellent performing speed for implementing non-binary LDPC decoder architectures. This paper proposes, a high throughput LDPC decoder through the implementation of fully parallel architecture and a reduction in the maximum iteration limit, needed for complete error correction. A Galois field of eight was utilized alongside a non-uniform quantization scheme, resulting in fewer bits per Log Likelihood Ratio (LLR) for the implementation. Verilog Hardware Description Language (HDL) was used in the description of the non-binary error control decoder. The propose decoder attained a throughput of 10Gbps at 400-MHz clock frequency when synthesized on a ZYNQ 7000 Series FPGA

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

International audienceThis paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design

Low-Power and Error-Resilient VLSI Circuits and Systems.

Efficient low-power operation is critically important for the success of the next-generation signal processing applications. Device and supply voltage have been continuously scaled to meet a more constrained power envelope, but scaling has created resiliency challenges, including increasing timing faults and soft errors. Our research aims at designing low-power and robust circuits and systems for signal processing by drawing circuit, architecture, and algorithm approaches. To gain an insight into the system faults due to supply voltage reduction, we researched the two primary effects that determine the minimum supply voltage (VMIN) in Intel’s tri-gate CMOS technology, namely process variations and gate-dielectric soft breakdown. We determined that voltage scaling increases the timing window that sequential circuits are vulnerable. Thus, we proposed a new hold-time violation metric to define hold-time VMIN, which has been adopted as a new design standard. Device scaling increases soft errors which affect circuit reliability. Through extensive soft error characterization using two 65nm CMOS test chips, we studied the soft error mechanisms and its dependence on supply voltage and clock frequency. This study laid the foundation of the first 65nm DSP chip design for a NASA spaceflight project. To mitigate such random errors, we proposed a new confidence-driven architecture that effectively enhances the error resiliency of deeply scaled CMOS and post-CMOS circuits. Designing low-power resilient systems can effectively leverage application-specific algorithmic approaches. To explore design opportunities in the algorithmic domain, we demonstrate an application-specific detection and decoding processor for multiple-input multiple-output (MIMO) wireless communication. To enhance the receive error rate for a robust wireless communication, we designed a joint detection and decoding technique by enclosing detection and decoding in an iterative loop to enhance both interference cancellation and error reduction. A proof-of-concept chip design was fabricated for the next-generation 4x4 256QAM MIMO systems. Through algorithm-architecture optimizations and low-power circuit techniques, our design achieves significant improvements in throughput, energy efficiency and error rate, paving the way for future developments in this area.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110323/1/uchchen_1.pd

State-of-the-art space mission telecommand receivers

Since their dawning, space communications have been among the strongest driving applications for the development of error correcting codes. Indeed, space-to-Earth telemetry (TM) links have extensively exploited advanced coding schemes, from convolutional codes to Reed-Solomon codes (also in concatenated form) and, more recently, from turbo codes to low-density parity-check (LDPC) codes. The efficiency of these schemes has been extensively proved in several papers and reports. The situation is a bit different for Earth-to-space telecommand (TC) links. Space TCs must reliably convey control information as well as software patches from Earth control centers to scientific payload instruments and engineering equipment onboard (O/B) spacecraft. The success of a mission may be compromised because of an error corrupting a TC message: a detected error causing no execution or, even worse, an undetected error causing a wrong execution. This imposes strict constraints on the maximum acceptable detected and undetected error rates

Flexible LDPC Decoder Architectures

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption

Codificación para corrección de errores con aplicación en sistemas de transmisión y almacenamiento de información

Tesis (DCI)--FCEFN-UNC, 2013Trata de una técnica de diseño de códigos de chequeo de paridad de baja densidad ( más conocidas por sigla en ingles como LDPC) y un nuevo algoritmo de post- procesamiento para la reducción del piso de erro

Spread-spectrum techniques for environmentally-friendly underwater acoustic communications

PhD ThesisAnthropogenic underwater noise has been shown to have a negative impact on marine life. Acoustic data transmissions have also been shown to cause behavioural responses in marine mammals. A promising approach to address these issues is through reducing the power of acoustic data transmissions. Firstly, limiting the maximum acoustic transmit power to a safe limit that causes no injury, and secondly, reducing the radius of the discomfort zone whilst maximising the receivable range. The discomfort zone is dependent on the signal design as well as the signal power. To achieve these aims requires a signal and receiver design capable of synchronisation and data reception at low-received-SNR, down to around −15 dB, with Doppler effects. These requirements lead to very high-ratio spread-spectrum signaling with efficient modulation to maximise data rate, which necessitates effective Doppler correction in the receiver structure. This thesis examines the state-of-the-art in this area and investigates the design, development and implementation of a suitable signal and receiver structure, with experimental validation in a variety of real-world channels. Data signals are designed around m-ary orthogonal signaling based on bandlimited carrierless PN sequences to create an M-ary Orthogonal Code Keying (M-OCK) modulation scheme. Synchronisation signal structures combining the energy of multiple unique PN symbols are shown to outperform single PN sequences of the same bandwidth and duration in channels with low SNR and significant Doppler effects. Signals and receiver structures are shown to be capable of reliable communications with band of 8 kHz to 16 kHz and transmit power limited to less than 170.8 dB re 1 μPa @ 1m, or 1W of acoustic power, over ranges of 10 km in sea trials, with low-received-SNR below −10 dB, at data rates of up to 140.69 bit/s. Channel recordings with AWGN demonstrated limits of signal and receiver performance of BER 10−3 at −14 dB for 35.63 bit/s, and −8.5 dB for 106.92 bit/s. Piloted study of multipath exploitation showed this performance could be improved to −10.5 dB for 106.92 bit/s by combining the energy of two arrival paths. Doppler compensation techniques are explored with experimental validation showing synchronisation and data demodulation at velocities over ranges of ±2.7m/s. Non-binary low density parity check (LDPC) error correction coding with M-OCK signals is investigated showing improved performance over Reed-Solomon (RS) coding of equivalent code rate in simulations and experiments in real underwater channels. The receiver structures are implemented on an Android mobile device with experiments showing live real-time synchronisation and data demodulation of signals transmitted through an underwater channel.UK Engineering and Physical Sciences Research Council (EPSRC): PhD Doctoral Training Account (DTA)

Multiple Parallel Concatenated Gallager Codes and Their Applications

Due to the increasing demand of high data rate of modern wireless communications, there is a significant interest in error control coding. It now plays a significant role in digital communication systems in order to overcome the weaknesses in communication channels. This thesis presents a comprehensive investigation of a class of error control codes known as Multiple Parallel Concatenated Gallager Codes (MPCGCs) obtained by the parallel concatenation of well-designed LDPC codes. MPCGCs are constructed by breaking a long and high complexity of conventional single LDPC code into three or four smaller and lower complexity LDPC codes. This design of MPCGCs is simplified as the option of selecting the component codes completely at random based on a single parameter of Mean Column Weight (MCW). MPCGCs offer flexibility and scope for improving coding performance in theoretical and practical implementation. The performance of MPCGCs is explored by evaluating these codes for both AWGN and flat Rayleigh fading channels and investigating the puncturing of these codes by a proposed novel and efficient puncturing methods for improving the coding performance. Another investigating in the deployment of MPCGCs by enhancing the performance of WiMAX system. The bit error performances are compared and the results confirm that the proposed MPCGCs-WiMAX based IEEE 802.16 standard physical layer system provides better gain compared to the single conventional LDPC-WiMAX system. The incorporation of Quasi-Cyclic QC-LDPC codes in the MPCGC structure (called QC-MPCGC) is shown to improve the overall BER performance of MPCGCs with reduced overall decoding complexity and improved flexibility by using Layered belief propagation decoding instead of the sum-product algorithm (SPA). A proposed MIMO-MPCGC structure with both a 2X2 MIMO and 2X4 MIMO configurations is developed in this thesis and shown to improve the BER performance over fading channels over the conventional LDPC structure