Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Ultra-short pulse compression using photonic crystal fibre

A short section of photonic crystal fibre has been used for ultra-short pulse compression. The unique optical properties of this novel medium in terms of high non-linearity and relatively small group velocity dispersion are shown to provide an ideal platform for the standard fibre pulse compression technique used directly on the nano-Joule output pulses from a commercial laser system. We report an order of magnitude reduction of the pulse width to 25 fs FWHM but predict a substantially improved performance with a dedicated fibre design. Good agreement is obtained with a simple model for the spectral broadening in the fibre

Special arod system studies seventh quarterly report

Phase lock loop advanced circuits, and technical summary for Airborne Range and Orbit Determination /AROD/ syste

Synthesizable delay line architectures for digitally controlled voltage regulators

Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies

Varactor-Tuned Dual-Mode Frequency Discriminator for Instantaneous Frequency Measurements

In this paper a novel varactor-tuned frequency discriminator that makes use of two tunable dual-mode microstrip resonators is demonstrated which doubles the discriminator tuning bandwidth. To prove its validity a prototype of the tunable dual-mode microstrip resonator is manufactured and the measured results are used to study the frequency discriminator response. This new approach can cover almost an octave of frequency range from 1.05 to 2 GHz with a sensitivity of 45 V/GHz and 21 V/GHz for the first and second mode, respectively.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

The Design and Linearization of 60GHz Injection Locked Power Amplifier

The RF power amplifier is one of the most critical blocks of transceivers, as it is expected to provide a suitable output power with high gain, efficiency and linearity. In this paper, a 60-GHz power amplifier based on an injection locked structure is demonstrated in a standard 65 CMOS technology. The PA core consists of a cross-coupled pair of NMOS transistors with an NMOS current source. This structure can achieve large output power and high PAE, but with poor linearity performance. In order to improve the linearity, several linearization techniques are investigated, including adaptive biasing and predistortion. The results show that the adaptive biasing technique can enlarge the linear operation region, but results in poor AM-PM performance. By instead using the predistortion technique, the AM-PM performance can be improved, but the linear region only extends slightly. Considering theses two techniques different advantages, we combine them together to improve not only the linear region but also the AM-PM performance. Finally, a common source amplifier is added as the first stage. With proper bias, the linear operation region is then effectively extended by 7.3 dB. This two stage power amplifier achieves large output power, high linearity and high PAE simultaneously. It delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.Since the invention of radio-frequency (RF) wireless communication more than 100 years ago, mobile phones and other wireless communications products for civilian consumption have developed rapidly. Nowadays, the demand for larger high data rate and capacities is rising sharply. The traditional wireless bandwidth is no longer able to meet some high-rate applications requirement. However, 60GHz wireless communication system is our solution, and up to 7 GHz unlicensed wide band around 60GHz is open to use across much of the world. Furthermore, the power amplifier (PA) is a critical part of any transmitter to convert the signal to higher power and drive the antenna. For power amplifiers, efficiency and linearity are most important. Power amplifiers with low efficiency will result in high level of heat dissipation. Linearity is a measure of the signal distortion, which consists of gain compression (AM-AM distortion) and phase distortion (AM-PM distortion). In this thesis work, an injection locked power amplifier is used to reduce the input driving requirements and improve the efficiency. Simulations have been performed for implementation in 65nm standard CMOS, which is a low-cost technology for fabrication of integrated circuits (chips). The injection locked technique means that a self-oscillating circuit is forced to run at the same frequency as the input signal. Furthermore, an integrated balun is added to transfer between single-ended and differential signals. The results show that this PA can achieve high efficiency but with poor linearity performance. In order to improve the linearity, different linearization techniques are investigated, including adaptive biasing and predistortion. Adaptive biasing is a feedback technique. At high output levels, the power amplifier has less gain, which leads to signal distortion. The adaptive biasing unit can sense the output power in real time and adjust the bias. The bias is then increased at increased output power in order to restore the power gain at high output levels. Predistortion is another linearization technique. A predistorter, which has a gain expansion characteristic, is then introduced before the PA to compensate for its gain reduction. Then, considering the advantages of these two linearization techniques, we combine them together to achieve even better results. Finally, a two-stage power amplifier is proposed by adding a common source amplifier as the first stage. The first stage can also produce a gain boost at the high output levels, and this expansion gain can be made to match the second-stage gain reduction very well. The simulation results show that the amplifier can achieve high linearity and efficiency at the same time

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans