THE USE OF DATA AUGMENTATION AND EXPLORATORY DATA ANALYSIS IN ENHANCING IMAGE FEATURES ON APPLE LEAF DISEASE DATASET

Apples are an essential commodity produced in Batu City, Malang. In 2017, Batu City, Malang, produced 19.1 tons of apples, while in 2018, Batu City, Malang, produced 15.9 tons of apples. It can be concluded that the decline in the number of apple harvests in Batu City, Malang. With the influence of technology in agriculture, the influence of technology can be used to detect diseases on leaves to overcome the decrease in the number of harvests. With the Image Augmentation method used in this study, the existing dataset can have 6x more features. So that the healthy category, which previously had 516 image features, now has 3096 image features, the scab category, which previously had 592 image features, now has 3552 image features and the rust category, which previously had 622 image features, now has 3732 image features. With a dataset with 3000 image features, the model to be made can have a higher accuracy value. The model can be said to be sturdy/sturdy/good, or the model to be made can carry out the classification process with a good level of accuracy

An Efficient Comparative Analysis of CNN-based Image Classification in the Jupyter Tool Using Multi-Stage Techniques

The main process of this image classification with a convolution neural network using deep learning model was performed in the programming language Python code in the Jupyter tool, mainly using the data set of IRS P-6 LISS IV from an Indian remote sensing satellite with a high resolution multi-spectral camera with around 5.8m from an 817 km altitude Delhi image. To classify the areas within the cropped image required to apply enhancement techniques, the image size was 1000 mb. To view this image file required high-end software for opening. For that, initially, ERDAS imaging software viewer was used for cropping into correct resolution pixels. based on that cropped image used for image classification with preprocessing for applying filters for enhancement. And with the convolution neural network model, required to train the sample images of the same pixels, was collected from the group of objects that were cropped. Then we needed to use image sample areas to train the model with learning rate and epoch rate to improve object detection accuracy using the Jupyter notebook tool with tensorflow and machine learning model produce the accuracy rate of 90.78%

Statistically Representative Metrology of Nanoparticles via Unsupervised Machine Learning of TEM Images

The morphology of nanoparticles governs their properties for a range of important applica tions. Thus, the ability to statistically correlate this key particle performance parameter is paramount in achieving accurate control of nanoparticle properties. Among several effective techniques for morphological characterization of nanoparticles, transmission electron microscopy (TEM) can pro vide a direct, accurate characterization of the details of nanoparticle structures and morphology at atomic resolution. However, manually analyzing a large number of TEM images is laborious. In this work, we demonstrate an efficient, robust and highly automated unsupervised machine learning method for the metrology of nanoparticle systems based on TEM images. Our method not only can achieve statistically significant analysis, but it is also robust against variable image quality, imaging modalities, and particle dispersions. The ability to efficiently gain statistically significant particle metrology is critical in advancing precise particle synthesis and accurate property control.Australia Research Council (ARC) IC210100056Ministerio de Economía y Competitividad TIN2014-55894-C2-RMinisterio de Economía y Competitividad TIN2017-88209-C2-2-

A flexible interconnection structure for reconfigurable FPGA dataflow applications

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Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

Real-time Vision-Based Lane Detection with 1D Haar Wavelet Transform on Raspberry Pi

Rapid progress is being made towards the realization of autonomous cars. Since the technology is in its early stages, human intervention is still necessary in order to ensure hazard-free operation of autonomous driving systems. Substantial research efforts are underway to enhance driver and passenger safety in autonomous cars. Toward that end GreedyHaarSpiker, a real-time vision-based lane detection algorithm is proposed for road lane detection in different weather conditions. The algorithm has been implemented in Python 2.7 with OpenCV 3.0 and tested on a Raspberry Pi 3 Model B ARMv8 1GB RAM coupled to a Raspberry Pi camera board v2. To test the algorithm’s performance, the Raspberry Pi and the camera board were mounted inside a Jeep Wrangler. The algorithm performed better in sunny weather with no snow on the road. The algorithm’s performance deteriorated at night time or when the road surface was covered with snow

Hexarray: A Novel Self-Reconfigurable Hardware System

Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm. The proposed reconfigurable hardware core is a systolic array, which is called HexArray. HexArray was constructed using processing elements with a redesigned architecture, called HexCells, which provide routing flexibility and support for hybrid reconfiguration schemes. The improved evolutionary algorithm is a genome-aware genetic algorithm (GAGA) that accelerates evolution. Guided by a fitness function the GAGA utilizes context-aware genetic operators to evolve solutions. The operators are genome-aware constrained (GAC) selection, genome-aware mutation (GAM), and genome-aware crossover (GAX). The GAC selection operator improves parallelism and reduces the redundant evaluations. The GAM operator restricts the mutation to the part of the genome that affects the selected output. The GAX operator cascades, interleaves, or parallel-recombines genomes at the cell level to generate better genomes. These operators improve evolution while not limiting the algorithm from exploring all areas of a solution space. The system was implemented on a SoC that includes a programmable logic (i.e., field-programmable gate array) to realize the HexArray and a processing system to execute the GAGA. A computationally intensive application that evolves adaptive filters for image processing was chosen as a case study and used to conduct a set of experiments to prove the developed system robustness. Through an iterative process using the genetic operators and a fitness function, the EHW system configures and adapts itself to evolve fitter solutions. In a relatively short time (e.g., seconds), HexArray is able to evolve autonomously to the desired filter. By exploiting the routing flexibility in the HexArray architecture, the EHW has a simple yet effective mechanism to detect and tolerate faulty cells, which improves system reliability. Finally, a mechanism that accelerates the evolution process by hiding the reconfiguration time in an “evolve-while-reconfigure” process is presented. In this process, the GAGA utilizes the array routing flexibility to bypass cells that are being configured and evaluates several genomes in parallel

Design and realization of a microassembly workstation

With the miniaturization of products to the levels of micrometers and the recent developments in microsystem fabrication technologies, there is a great need for an assembly process for the formation of complex hybrid microsystems. Integration of microcomponents made up of different materials and manufactured using different micro fabrication techniques is still a primary challenge since some of the fundamental problems originating from the small size of parts to be manipulated, high precision necessity and specific problems of the microworld in that field are still not fully investigated. In this thesis, design and development of an open-architecture and reconfigurable microassembly workstation for efficient and reliable assembly of micromachined parts is presented. The workstation is designed to be used as a research tool for investigation of the problems in microassembly. The development of such a workstation includes the design of: (i) a manipulation system consisting of motion stages providing necessary travel range and precision for the realization of assembly tasks, (ii) a vision system to visualize the microworld and the determination of the position and orientation of micro components to be assembled, (iii) a robust control system and necessary fixtures for the end effectors that allow easy change of manipulation tools and make the system ready for the desired task. In addition tele-operated and semi-automated assembly concepts are implemented. The design is verified by implementing tasks in various ranges for micro-parts manipulation. The versatility of the workstation is demonstrated and high accuracy of positioning is shown

Discrete Wavelet Transforms

The discrete wavelet transform (DWT) algorithms have a firm position in processing of signals in several areas of research and industry. As DWT provides both octave-scale frequency and spatial timing of the analyzed signal, it is constantly used to solve and treat more and more advanced problems. The present book: Discrete Wavelet Transforms: Algorithms and Applications reviews the recent progress in discrete wavelet transform algorithms and applications. The book covers a wide range of methods (e.g. lifting, shift invariance, multi-scale analysis) for constructing DWTs. The book chapters are organized into four major parts. Part I describes the progress in hardware implementations of the DWT algorithms. Applications include multitone modulation for ADSL and equalization techniques, a scalable architecture for FPGA-implementation, lifting based algorithm for VLSI implementation, comparison between DWT and FFT based OFDM and modified SPIHT codec. Part II addresses image processing algorithms such as multiresolution approach for edge detection, low bit rate image compression, low complexity implementation of CQF wavelets and compression of multi-component images. Part III focuses watermaking DWT algorithms. Finally, Part IV describes shift invariant DWTs, DC lossless property, DWT based analysis and estimation of colored noise and an application of the wavelet Galerkin method. The chapters of the present book consist of both tutorial and highly advanced material. Therefore, the book is intended to be a reference text for graduate students and researchers to obtain state-of-the-art knowledge on specific applications