Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches

In this study, a novel structure for cascade multilevel inverter is presented. The proposed inverter can generate all possible DC voltage levels with the value of positive and negative. The proposed structure results in reduction of switches number, relevant gate driver circuits and also the installation area and inverter cost. The suggested inverter can be used as symmetric and asymmetric structures. Comparing the peak inverse voltage and losses of the proposed inverter with conventional multilevel inverters show the superiority of the proposed converter. The operation and good performance of the proposed multilevel inverter have been verified by the simulation results of a single-phase nine-level symmetric and 17-level asymmetric multilevel inverter and experimental results of a nine-level and 17-level inverters. Simulation and experimental results confirmed the validity and effectiveness performance of the proposed inverter

Multilevel Converters: An Enabling Technology for High-Power Applications

| Multilevel converters are considered today as the state-of-the-art power-conversion systems for high-power and power-quality demanding applications. This paper presents a tutorial on this technology, covering the operating principle and the different power circuit topologies, modulation methods, technical issues and industry applications. Special attention is given to established technology already found in industry with more in-depth and self-contained information, while recent advances and state-of-the-art contributions are addressed with useful references. This paper serves as an introduction to the subject for the not-familiarized reader, as well as an update or reference for academics and practicing engineers working in the field of industrial and power electronics.Ministerio de Ciencia y Tecnología DPI2001-3089Ministerio de Eduación y Ciencia d TEC2006-0386

A New Symmetric/Asymmetric Multilevel Inverter Based on Cascaded Connection of Sub-Multilevel Units Aiming less Switching Components and Total Blocked Voltage

In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure the desired output voltage can be produced by considering a series connection of a novel sub-multilevel module. This structure can be designed in both the symmetric and asymmetric topologies. The proposed structure has superior condition in terms of semiconductor switches and drivers count as well as switching loss. Additionally, the Total Blocked Voltage (TBV) of the proposed converter is compared with the conventional and the novel converters. This topology is studied by symmetric as well as asymmetric topologies through simulations in Matlab/Simulink environment as well as experiments by a laboratory prototype

Reduced switch multilevel inverter topologies for renewable energy sources

This article proposes two generalized multilevel inverter configurations that reduce the number of switching devices, isolated DC sources, and total standing voltage on power switches, making them suitable for renewable energy sources. The main topology is a multilevel inverter that handles two isolated DC sources with ten power switches to create 25 voltage levels. Based on the main proposed topology, two generalized multilevel inverters are introduced to provide flexibility in the design and to minimize the number of elements. The optimal topologies for both extensive multilevel inverters are derived from different design objectives such as minimizing the number of elements (gate drivers, DC sources), achieving a large number of levels, and minimizing the total standing voltage. The main advantages of the proposed topologies are a reduced number of elements compared to those required by other existing multilevel inverter topologies. The power loss analysis and standalone PV application of the proposed topologies are discussed. Experimental results are presented for the proposed topology to demonstrate its correct operation. © 2013 IEEE

Power loss investigation in HVDC for cascaded H-bridge multilevel inverters (CHB-MLI)

In the last decade, the use of voltage-source multilevel inverters in industrial and utility power applications has been increased significantly mainly due to the many advantages of multilevel inverters, compared to conventional two level inverters. These advantages include: 1) higher output voltage at low switching frequency, 2) low voltage stress (dv/dt), 3) lower total harmonic distortion (THD), 4) less electro-magnetic interference (EMI), 5) smaller output filter, and 6) higher fundamental output. However, the computation of multilevel inverter power losses is much more complicated compared to conventional two level inverters. This paper presents a detailed investigation of CHB-MLI losses for HVDC. Different levels, and IGBT switching devices have been considered in the study. The inverter has been controlled using selective harmonic elimination in which the switching angles were determined using the Genetic Algorithm (GA). MATLAB-SIMULINK is used for the modelling and simulation. This investigation should result in a deeper knowledge and understanding of the performance of CHB-MLI using different IGBT switching devices

A Review on Multilevel Inverter Topologies

In this paper, a brief review of the multilevel inverter (MLI) topologies is presented. The two-level Voltage Source Inverter (VSI) requires a suitable filter to produce sinusoidal output waveforms. The high-frequency switching and the PWM method are used to create output waveforms with the least amount of ripples. Due to the switching losses, the traditional two-level inverter has some restrictions when running at high frequencies. For addressing this problem, multilevel inverters (MLI) with lower switching frequencies and reduced total harmonic distortion (THD) are employed, eliminating the requirement for filters and bulky transformers. Furthermore, improved performance at the high switching frequency, higher power quality (near to pure sinusoidal), and fewer switching losses are just a few of the benefits of MLI inverters. However, each switch has to have its own gate driver for implementing MLI, which adds to the system's complexity. Therefore, reducing the number of switches of MLI is necessary. This paper presents a review of some of the different current topologies using a lower number of switches. Doi: 10.28991/ESJ-2022-06-01-014 Full Text: PD

Cascaded Converters For Integration And Management Of Grid Level Energy Storage Systems

ABSTRACT CASCADED CONVERTERS FOR INTEGRATION AND MANAGEMENT OF GRID-LEVEL ENERGY STORAGE SYSTEMS by ZUHAIR ALAAS December 2017 Advisor: Dr. Caisheng Wang Major: ELECTRICAL ENGINEERING Degree: Doctor of Philosophy This research work proposes two cascaded multilevel inverter structures for BESS. The gating and switching control of switching devices in both inverter typologies are done by using a phase-shifted PWM scheme. The first proposed isolated multilevel inverter is made up of three-phase six-switch inverter blocks with a reduced number of power components compared with traditional isolated CHB. The suggested isolated converter has only one battery string for three-phase system that can be used for high voltage and high power applications such as grid connected BESS and alternative energy systems. The isolated inverter enables dq frame based simple control and eliminates the issues of single-phase pulsating power, which can cause detrimental impacts on certain dc sources. Simulation studies have been carried out to compare the proposed isolated multi-level inverter with an H-bridge cascaded transformer inverter. The simulation results verified the performance of the isolated inverter. The second proposed topology is a Hierarchal Cascaded Multilevel Converter (HCMC) with phase to phase SOC balancing capability which also for high voltage and high power battery energy storage systems. The HCMC has a hybrid structure of half-bridge converters and H-bridge inverters and the voltage can be hierarchically cascaded to reach the desired value at the half-bridge and the H-bridge levels. The uniform SOC battery management is achieved by controlling the half-bridge converters that are connected to individual battery modules/cells. Simulation studies and experimental results have been carried on a large scale battery system under different operating conditions to verify the effectiveness of the proposed inverters. Moreover, this dissertation presents a new three-phase SOC equalizing circuit, called six-switch energy-level balancing circuit (SSBC), which can be used to realize uniform SOC operation for full utilization of the battery capacity in proposed HCMC or any CMI inverter while keeping balanced three-phase operation. A sinusoidal PWM modulation technique is used to control power transferring between phases. Simulation results have been carried out to verify the performance of the proposed SSBC circuit of uniform three-phase SOC balancing

Design, Optimization and Implementation of a High Frequency Link Multilevel Cascaded Inverter

This thesis presents a new concept of cascaded MLI (CMLI) device reduction by utilizing low and high frequency transformer link. Two CMLI topologies, symmetric and asymmetric are proposed. Compared with counterpart CMLI topologies available in the literatures, the proposed two inverter topologies in this thesis have the advantages of utilizing least number of electronic components without compromising overall performance particularly when a high number of levels is required in the output voltage waveform

Asymmetric Cascaded Multilevel Inverter with Unequal Dc Sources using SPWM and MSVPWM Topologies

This paper introduces the modeling design and simulation of seven and thirteen levels cascaded asymmetric multilevel inverter (MLI) with reduced number of switches.  MLI is the most efficient energy converters which are essentially appropriated for high power applications with decrease total harmonics distortion (THD). MLI doesn't only get high power in the output but it is also utilized in renewable energy resources such as fuel cells, wind and photovoltaic cells. This paper principally focuses on a hybrid cascaded MLI with two and three unequal dc supplies which decreases the number of semiconductor power switches. Sinusoidal PWM (SPWM) and modified space vector PWM (MSVPWM) techniques are used to improve an ac output with reduced THD. The gating pulses for seven and thirteen level hybrid cascaded converter using SPWM and MSVPWM techniques are introduced. The results of these proposed modulation strategies reduce the percentage magnitude of THD. The performance of the proposed SPWM and MSVPWM topologies are verified using seven and thirteen levels cascaded asymmetric MLI via simulink/matlab. Keywords: Sinusoidal Pulse Width Modulation (SPWM), Modified Space Vector Pulse Width Modulation (MSVPWM), Multilevel Inverter (MLI), Total Harmonics Distortion (THD)

Cascaded single-phase, PWM multilevel inverter with boosted output voltage

Splitting of a dc voltage source with two capacitors has been the approach in generating 5-level output voltage with single- and three-phase full-bridge circuits and added bidirectional switch. Associated with this configuration is the problem of voltage imbalance between the splitting capacitors. In addition, the inverter output voltage magnitude is obviously limited to the value of the split input voltage source. Presented in this paper is a unit topology for single-phase 5-level multilevel inverter, MLI. It simply consists of a full-bridge circuit, a capacitor, charge-discharge unit and a dc source. The charge-discharge unit with the capacitor is the interface between the full-bridge and the dc source. The proposed unit cell can generate a 5-level output voltage waveform whose peak value is twice the input voltage value. For higher output voltage level, a cascaded structure of the developed unit cell is presented. Comparing the proposed inverter with CHB inverter and some recent developed MLI topologies, it is found that the proposed inverter configuration generates higher output voltage value, at reduced component-count, than other topologies, for a specified number of dc input voltages. For two cascaded modules, simulation and experimental verifications are carried out on the proposed inverter topology for an R-L load. Keywords: Cascaded multilevel, Inverter, total harmonic distortion, topologies, wavefor