Top-down Si nanowire technology in discrete charge storage nonvolatile memory application

Ph.DDOCTOR OF PHILOSOPH

Semiconductor Nanowire MOSFETs and Applications

Semiconductor nanowires have aroused a lot of scientific interest and have been regarded as one of the most promising candidates that would make possible building blocks in future nanoscale devices and integrated circuits. Employing nanowire as metal‐oxide‐semiconductor field‐effect transistor (MOSFET) channel can enable a gate‐surrounding structure allowing an excellent electrostatic gate control over the channel for reducing the short‐channel effects. This chapter introduces the basic physics of semiconductor nanowires and addresses the problem of how to synthesize semiconductor nanowires with low‐cost, high‐efficiency and bottom‐up approaches. Effective integration of nanowires in modern complementary metal‐oxide‐semiconductor (CMOS) technology, specifically in MOSFET devices, and non‐volatile memory applications is also reviewed. By extending the nanowire MOSFET structure into a universal device architecture, various novel semiconductor materials can be investigated. Semiconductor nanowire MOSFETs have been proved to be a strong and useful platform to study the physical and electrical properties of the novel material. In this chapter, we will also review the investigations on topological insulator materials by employing the nanowire field‐effect transistor (FET) device structure

High-Performance Silicon Nanowire Electronics

This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators. Both SiNW surface treatments and dielectric annealing are reported for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV), high carrier mobilities (~269 cm2/V•s), and low subthreshold swing (~80 mV/dec). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs is explored as well. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. A set of novel charge-trap non-volatile memory devices based on high-performance SiNW FETs are well investigated. These memory devices integrate Fe2O3 quantum dots (FeO QDs) as charge storage elements. A template-assisted assembly technique is used to align FeO QDs into a close-packed, ordered matrix within the trenches that separate highly aligned SiNWs, and thus store injected charges. A Fowler-Nordheim tunneling mechanism describes both the program and erase operations. The memory prototype demonstrates promising characteristics in terms of large threshold voltage shift (~1.3 V) and long data retention time (~3 × 106 s), and also allows for key components to be systematically varied. For example, varying the size of the QDs indicates that larger diameter QDs exhibit a larger memory window, suggesting the QD charging energy plays an important role in the carrier transport. The device temperature characteristics reveal an optimal window for device performance between 275K and 350K. The flexibility of integrating the charge-trap memory devices with the SiNW logic devices offers a low-cost embedded non-volatile memory solution. A building block for a SiNW-based field-programmable gate array (FPGA) is proposed in the future work.</p

Redox-Active Molecules for Novel Nonvolatile Memory Applications

The continuous complementary metal‐oxide‐semiconductor (CMOS) scaling is reaching fundamental limits imposed by the heat dissipation and short‐channel effects, which will finally stop the increase of integration density and the MOSFET performance predicted by Moore’s law. Molecular technology has been aggressively pursued for decades due to its potential impact on future micro‐/nanoelectronics. Molecules, especially redox‐active molecules, have become attractive due to their intrinsic redox behavior, which provides an excellent basis for low‐power, high‐density, and high‐reliability nonvolatile memory applications. This chapter briefly reviews the development of molecular electronics in the application of nonvolatile memory. From the mechanical motion of molecules in the Langmuir‐Blodgett film to new families of redox‐active molecules, memory devices involving hybrid molecular technology have shown advantageous potential in fast speed, low‐power, and high‐density nonvolatile memory and will lead to promising on‐chip memory as well as future portable electronics applications

High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer

Abstract-This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded chargetrapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10 4 s at 150 • C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications. Index Terms-Nanocrystal (NC), nonvolatile memory (NVM), thin-film transistor (TFT)

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

실리콘 기반의 전하 트랩 메모리를 이용한 시냅스의 가소성 및 학습 기능 구현

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 이종호.The development of an energy efficient and highly integrated electronic synapse is an important step in the effort to mimic the adaptive learning and memory in a biological neural network. Recently, several types of two-terminal memristors have been proposed to emulate biologically inspired synaptic functions using various components such as atomic switches, phase-change memory (PCM), and resistive switching devices. However, these two terminal devices require one select device per cell in a cell array to imitate a synapse-neuron network. Moreover, they need to be improved in terms of reliability, repeatability and processing complexity. In this thesis, we propose a new silicon-based charge trap memory device with an Al2O3/HfO2/Si3N4 (A/H/N) gate stack to realize the imitation of memory features in a biological synapse. In a fabricated capacitor having the proposed gate stack, short-term plasticity (STP) and long-term potentiation (LTP) properties with their transition are demonstrated, which are similar to the behavior of biological synapses. A single charge trapping layer (Si3N4) on silicon interface induces fast charge loss by trap-assisted tunneling (TAT) or direct tunneling. In addition, there is no remarkable pulse interval dependence when repeated input pulses are applied, in which the pulse amplitude and width are same. However, more frequent input pulses leads to larger current changes with longer retention property when HfO2 layer is inserted on Si3N4 layer as a second charge trapping layer. It is originated from the deep trap level (ET) in HfO2 layer leading to a transition into long-term memory. Lastly, we proposed a pair of pre- and post-synaptic spike scheme for the synaptic device and STDP property was demonstrated from experimental data. This suggested architecture has remarkable advantages, including high uniformity over a large area, excellent reliability, the use of CMOS-compatible materials, and easy integration with CMOS circuits.Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Major factors influencing retention properties 2 1.3 Si3N4 and HfO2 for charge trap layers 5 1.4 Design of gate stack for synaptic device 7 1.5 Thesis organization 9 Chapter 2. Al2O3/HfO2/Si3N4 (A/H/N) gate stack 11 2.1 Introduction 11 2.2 Fabrication process for a capacitor 12 2.3 Measurement setup 14 2.4 C-V characteristics 15 2.5 Transient properties with C-t measurements 20 Chapter 3. Analysis of charge trapping and retention mechanism 30 3.1 Introduction 30 3.2 Measurement and discussion 31 Chapter 4. Synaptic characteristics in a FET device 41 4.1 Fabrication process of a FET device 41 4.2 Characteristics of SiO2/Si3N4 (O/N) stack 44 4.3 Scaling of Al2O3/HfO2/Si3N4 (A/H/N) stack 54 4.4 Spike-timing-dependent plasticity (STDP) 65 Chapter 5. Conclusions 70 Appendix. Spatial trap distribution near silicon interface 71 3.1 Introduction 71 3.2 Measurement results and discussion. 75 Bibliography 80 List of Publication 92 Abstract in Korean 94Docto

High Performance Lateral Phase Change Random Access Memory

Ph.DDOCTOR OF PHILOSOPH

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement