Optimization of performance and reliability of HZO-based capacitors for ferroelectric memory applications

In an era in which the amount of produced and stored data continues to exponentially grow, standard memory concepts start showing size, power consumption and costs limitation which make the search for alternative device concepts essential. Within a context where new technologies such as DRAM, magnetic RAM, resistive RAM, phase change memories and eFlash are explored and optimized, ferroelectric memory devices like FeRAM seem to showcase a whole range of properties which could satisfy market needs, offering the possibility of creating a non-volatile RAM. In fact, hafnia and zirconia-based ferroelectric materials opened up a new scenario in the memory technology scene, overcoming the dimension scaling limitations and the integration difficulties presented by their predecessors perovskite ferroelectrics. In particular, HfₓZr₁₋ₓO₂ stands out because of high processing flexibility and ease of integration in the standard semiconductor industry process flows for CMOS fabrication. Nonetheless, further understanding is necessary in order tocorrelate device performance and reliability to the establishment of ferroelectricity itself. The aim of this work is to investigate how the composition of the ferroelectric oxide, together with the one of the electrode materials influence the behavior of a ferroelectric RAM. With this goal, different process parameters and reliability properties are considered and an analysis of the polarization reversal is performed. Starting from undoped hafnia and zirconia and subsequently examining their intermixed system, it is shown how surface/volume energy contributions, mechanical stress and oxygen-related defects all concur in the formation of the ferroelectric phase. Based on the process optimization of an HfₓZr₁₋ₓO₂-based capacitor performed within these pages, a 64 kbit 1T1C FeRAM array is demonstrated by Sony Semiconductor Solutions Corporation which shows write voltage and latency as low as 2.0 V and 16 ns, respectively. Outstanding retention and endurance performances are also predicted, which make the addressed device an extremely strong competitor in the semiconductor scene

Dielectric relaxation and frequency dependence of Hf02 doped by lanthanide elements

The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology requires the replacement of SiO2 with gate dielectrics that have a high dielectric constant (k). When the SiO2 gate thickness was reduced below 1.4 nm, electron tunneling effects and high leakage currents occurred which presented serious obstacles for the reliability issue in terms of metal-oxide-semiconductor field-effect transistor (MOSFET) devices. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology has been a very active research area. Frequency dispersion of high-k dielectrics was commonly observed and classified into two parts: extrinsic and intrinsic causes. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such as the effects of the lossy interfacial layer (between the high-k thin film and silicon substrate) and the parasitic effects. The significance of parasitic effects (including series resistance and the back metal contact of the metal-oxide-semiconductor (MOS) capacitor) on frequency dispersion was studied. The effect of the lossy interfacial layer on frequency dispersion was investigated and modeled using a dual frequency technique. The effect of surface roughness on frequency dispersion is also investigated. Several mathematical models were discussed to describe the dielectric relaxation of high-k dielectrics. Some of the relaxation behavior can be modeled using the Curie-von Schweidler (CS) law, the Kohlrausch-Williams-Watts (KWW) relationship and the Havriliak-Negami (HN) relationship. Other relaxation models were also introduced. For the physical mechanism, dielectric relaxation was found to be related to the degree of polarization, which was dependent on the structure of the high-k material. The degree of polarization was attributed to the enhancement of the correlations among polar nano-scale size domain within the materials. The effect of grain size for the high-k materials' structure mainly originated from higher surface stress in smaller grain size due to its higher concentration of grain boundary

Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry

Impact of Chemistry and Processing of Atomic Layer Deposited Dielectrics on Silicon

Oxide/semiconductor interfaces are ubiquitous in modern electronics. If these interfaces are of poor quality (e.g., large amount of electronic traps) or possess traits that are undesirable (e.g. fixed charge in metal oxide semiconductor field effect transistors, MOSFETs), the device will not function properly or at all. Atomic layer deposition (ALD) has been shown to produce films with a wide variety of properties, due in part to the variability in processing parameters, such that thin films can be grown for a wide variety of applications.One such variance in process parameters is the chemistry utilized to grow ALD films. Typically, Al2O3 films are grown with trimethylaluminum (TMA) and water. Non-hydrolytic ALD (NHALD) utilizes less oxidative precursors than water, which can affect the film and interface properties. I have shown that using isopropyl alcohol (IPA) instead of water as the oxygen precursor in the ALD growth of Al2O3 results in films with a larger fixed charge (NF), but also a higher concentration of carbon impurities that lead to a higher amount of electronic defects at the interface (Dit) and even in the oxide bulk. Preliminary work was done to make hybrid traditional/NHALD films by which the volume density of electronic traps can be measured and the overall film properties can be modified.Another parameter by which film properties can be modified is the deposition temperature during ALD. I have deposited films using temperatures ranging from 50°C to 300°C on both hydrogen-terminated silicon and silicon containing a native oxide. Fixed charge and interface trap state density was measured on metal oxide capacitor (MOSCap) structures. We have shown that fixed charge magnitude is low at high deposition temperatures and at 50°C, with a maximum at ~100°C. We have also shown that oxides deposited at 50°C contain a defect state that corresponds to silicon dangling bonds at the surface. The presence of dangling bonds implies that insufficient hydrogen is present to passivate them, and the low NF implies that less excess oxygen is present to contribute to NF. This is surprising as films deposited at low temperatures contain more –OH groups trapped in the film. However, Al2O3 deposited at lower temperatures is less dense and therefore allows more –OH groups to effuse from the film during annealing, thus explaining the apparent hydrogen and oxygen deficiency.In addition to MOSCap structures, I have also made and measured MOS diodes, which have the same structure as MOSCaps but contain an oxide layer that is less than 2.5 nm, thus allowing direct tunneling of carriers between the metal and semiconductor. These structures are useful in low-resistance metal/semiconductor contacts and as rectifying junctions in metal-insulator-semiconductor photovoltaics (MISPVs). Using numerical simulations and analytical expressions, the Schottky barrier height (ϕB) of the MOS diodes should rely both on the fixed charge and oxide thickness. By making devices with high and low NF magnitudes (annealed and as-deposited, respectively) and with different oxide thicknesses, the ability of the fixed charge to modify the ϕB was shown to not exist. Our data instead imply that electronic dipoles at the Al2O3/SiO2 interface control the barrier height. The barrier height trends are explained by dipoles that depend on the thickness and chemical character of the SiO2 interface layer. I have carried out some preliminary investigations of the Al2O3/SiO2 dipole for oxides using water, IPA, and O3 as oxygen precursors as well as just begin an experiment to measure the presence (or absence) of a dipole at the Al2O3/TiO2 interface

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured

Effect of forming gas annealing on the degradation properties of Ge-based MOS stacks

The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge–III-V hybrid devices.Fil: Aguirre, Fernando Leonel. Universidad Tecnológica Nacional. Facultad Regional Buenos Aires; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Pazos, Sebastián Matías. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional. Facultad Regional Buenos Aires; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional. Facultad Regional Buenos Aires; ArgentinaFil: Fadida, S.. Technion - Israel Institute of Technology; IsraelFil: Winter, R.. Technion - Israel Institute of Technology; IsraelFil: Eizenberg, M.. Technion - Israel Institute of Technology; Israe

Material development of doped hafnium oxide for non-volatile ferroelectric memory application

Seit der Entdeckung von Ferroelektrizität in Hafniumoxid stellt es aufgrund seiner Prozesskompatibilität im Bereich der Mikroelektronik sowie seiner besonderen Eigenschaften ein wachsendes Forschungsfeld dar. Im Speziellen wird die Anwendung in nicht-flüchtigen Speichern, in neuromorphen Bauelementen sowie in piezo-/pyroelektrischen Sensoren untersucht. Jedoch ist das Verhalten von ferroelektrischem Hafniumoxid im Vergleich zu Ferroelektrika mit Perovskit-Struktur nicht im Detail verstanden. Zudem spielen Prozesseinflüsse während und nach der Abscheidung eine entscheidende Rolle für die Materialeigenschaften aufgrund der metastabilen Natur der ferroektrischen Phase in diesem Materialsystem. In dieser Arbeit werden die grundlegenden physikalischen Eigenschaften von Hafniumoxid, Prozesseinflüsse auf die Mikrostruktur und Zuverlässigkeitsaspekte von nicht-flüchtigen sowie neuromorphen Bauelementen untersucht. Im Bezug auf die physikalischen Eigenschaften zeigen sich hier deutliche Belege für ferroelastische 90° Domänenwandbewegungen in Hafniumoxid-basierten Dünnschichten, welche in einem ähnlichen Verhalten wie ein Antiferroelektrikum resultieren. Weiterhin wird über die Entdeckung von einer mittels elektrischem Feld induzierten Kristallisation in diesem Materialsystem berichtet. Für die Charakterisierung der Mikrostruktur wird als neue Methode Transmissions-Kikuchi-Diffraktion eingeführt, welche eine detaillierte Untersuchung der lokalen kristallographischen Phase, Orientierung und Gefügestruktur ermöglicht. Hierbei zeigen sich deutliche Vorzugsorientierungen in Abhängigkeit des Substrates, der Dotierstoffkonzentration sowie der Glühtemperatur. Auf Basis dieser Ergebnisse lassen sich die beobachteten Zuverlässigkeitsverhalten in Bauelementen erklären und mittels Defektkontrolle weiter optimieren. Schließlich wird das Verhalten in neuromorphen Bauelementen untersucht und Leitlinien für Prozess- und Bauelementoptimierung gegeben.:Abstract i Abstract ii List of Figures vi List of Tables x Acronyms xi Symbols xiv 1 Introduction 1 2 Theoretical background 3 2.1 Behavior of ferroelectric materials 3 2.1.1 Phase transitions at the Curie temperature 4 2.1.2 Domains, domain walls, and microstructure 5 2.2 Ferroelectricity in HfO2 6 2.2.1 Thermodynamics and kinetics 8 2.2.2 Antiferroelectric-like behavior, wake-up effect, and fatigue 11 2.2.3 Piezo- and pyroelectric effects 13 2.3 Ferroelectric FETs 13 2.3.1 Endurance, retention and variability 14 2.3.2 Neuromorphic devices 15 3 Methodology 17 3.1 Electrical analysis 17 3.1.1 Capacitors 17 3.1.2 FeFETs 19 3.2 Structural and chemical analysis 20 3.2.1 Grazing-incident X-ray diffraction (GIXRD) 20 3.2.2 Transmission electron microscopy (TEM) 20 3.2.3 Time-of-flight secondary ion mass spectrometry (ToF-SIMS) 21 3.3 Transmission Kikuchi diffraction 21 3.4 Sample preparation 23 4 The physics of ferroelectric HfO2 25 4.1 Ferroelastic switching 25 4.2 Electric field-induced crystallization 30 5 Microstructure engineering 33 5.1 Microstructure and ferroelectric domains in HfO2 33 5.2 Doping influences 34 5.2.1 Zr doping (similar ionic radius) 35 5.2.2 Si doping (smaller ionic radius) 43 5.2.3 La doping (larger ionic radius) 50 5.2.4 Co-doping 50 5.3 Annealing influences 53 5.4 Interlayer influences 58 5.5 Interface layer influences 62 5.5.1 Structural differences in the HfO2 layer 63 5.5.2 Interactions of the interface and HfO2 layer 67 5.5.3 Substrate-driven changes in the Si-doping profile 73 5.6 Phenomenological wake-up behaviors and process guidelines 77 6 HfO2-based ferroelectric FETs 81 6.1 Endurance, retention and variability 81 6.1.1 Analytic model of HfO2-based FeFETs 84 6.1.2 Endurance improvements by interface fluorination 94 6.2 Neuromorphic devices and circuits 98 6.2.1 Current peroclation paths in FeFETs 100 6.2.2 Material and stack influences on synaptic devices 105 6.2.3 Reliability aspects of synaptic devices 106 7 Conclusion and outlook 109 Appendix 142 Density-functional-theory calculations 142 Supplementary Figures 143 Publications 145 Acknowledgment 156 Declaration 158The discovery of ferroelectricity in hafnium oxide spurred a growing research field due to hafnium oxides compatibility with processes in microelectronics as well as its unique properties. Notably, its application in non-volatile memories, neuromorphic devices as well as piezo- and pyroelectric sensors is investigated. However, the behavior of ferroelectric hafnium oxide is not understood into depth compared to common perovskite structure ferroelectrics. Due the the metastable nature of the ferroelectric phase, process conditions have a strong influence during and after its deposition. In this work, the physical properties of hafnium oxide, process influences on the microstructure as well as reliability aspects in non-volatile and neuromorphic devices are investigated. With respect to the physical properties, strong evidence is provided that the antiferroelectric-like behavior in hafnium oxide based thin films is governed by ferroelastic 90° domain wall movement. Furthermore, the discovery of an electric field-induced crystallization process in this material system is reported. For the analysis of the microstructure, the novel method of transmission Kikuchi diffraction is introduced, allowing an investigation of the local crystallographic phase, orientation and grain structure. Here, strong crystallographic textures are observed in dependence of the substrate, doping concentration and annealing temperature. Based on these results, the observed reliability behavior in the electronic devices is explainable and engineering of the present defect landscape enables further optimization. Finally, the behavior in neuromorphic devices is explored as well as process and design guidelines for the desired behavior are provided.:Abstract i Abstract ii List of Figures vi List of Tables x Acronyms xi Symbols xiv 1 Introduction 1 2 Theoretical background 3 2.1 Behavior of ferroelectric materials 3 2.1.1 Phase transitions at the Curie temperature 4 2.1.2 Domains, domain walls, and microstructure 5 2.2 Ferroelectricity in HfO2 6 2.2.1 Thermodynamics and kinetics 8 2.2.2 Antiferroelectric-like behavior, wake-up effect, and fatigue 11 2.2.3 Piezo- and pyroelectric effects 13 2.3 Ferroelectric FETs 13 2.3.1 Endurance, retention and variability 14 2.3.2 Neuromorphic devices 15 3 Methodology 17 3.1 Electrical analysis 17 3.1.1 Capacitors 17 3.1.2 FeFETs 19 3.2 Structural and chemical analysis 20 3.2.1 Grazing-incident X-ray diffraction (GIXRD) 20 3.2.2 Transmission electron microscopy (TEM) 20 3.2.3 Time-of-flight secondary ion mass spectrometry (ToF-SIMS) 21 3.3 Transmission Kikuchi diffraction 21 3.4 Sample preparation 23 4 The physics of ferroelectric HfO2 25 4.1 Ferroelastic switching 25 4.2 Electric field-induced crystallization 30 5 Microstructure engineering 33 5.1 Microstructure and ferroelectric domains in HfO2 33 5.2 Doping influences 34 5.2.1 Zr doping (similar ionic radius) 35 5.2.2 Si doping (smaller ionic radius) 43 5.2.3 La doping (larger ionic radius) 50 5.2.4 Co-doping 50 5.3 Annealing influences 53 5.4 Interlayer influences 58 5.5 Interface layer influences 62 5.5.1 Structural differences in the HfO2 layer 63 5.5.2 Interactions of the interface and HfO2 layer 67 5.5.3 Substrate-driven changes in the Si-doping profile 73 5.6 Phenomenological wake-up behaviors and process guidelines 77 6 HfO2-based ferroelectric FETs 81 6.1 Endurance, retention and variability 81 6.1.1 Analytic model of HfO2-based FeFETs 84 6.1.2 Endurance improvements by interface fluorination 94 6.2 Neuromorphic devices and circuits 98 6.2.1 Current peroclation paths in FeFETs 100 6.2.2 Material and stack influences on synaptic devices 105 6.2.3 Reliability aspects of synaptic devices 106 7 Conclusion and outlook 109 Appendix 142 Density-functional-theory calculations 142 Supplementary Figures 143 Publications 145 Acknowledgment 156 Declaration 15

Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (60Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO2/Al2O3 stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O2 and N2 annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O2 annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance

Monolithic integration of crystalline oxides on silicon and germanium using atomic layer deposition

textInside your microelectronic devices there are up to a billion transistors working in flawless operation. Silicon has been the workhorse semiconductor used for the transistor; however, there must be a transition to materials other than silicon, such as germanium, with future device sizes. In addition, new dielectric oxide materials are needed. My research has examined a type of crystalline oxide, known as a perovskite, which is selected for its ability to bond chemically to Si and Ge, and eliminate the electrical defects that affect performance. Many perovskite oxides are lattice-matched to the Si (001) and Ge (001) surface spacing, enabling heteroepitaxy. To date, the majority of research on crystalline oxides integrated with semiconductors has been based on strontium titanate, SrTiO3, epitaxially grown on Si (001) by molecular beam epitaxy. Alternative low-temperature growth methods, such as atomic layer deposition (ALD), offer both practical and economic benefits for the integration of crystalline oxides on semiconductors. My initial research informed the broader community that four unit cells (~1.5 nm) of SrTiO3 are required to enable heteroepitaxy on Si. The research has also shown that heteroepitaxial layers can be monolithically integrated with Si (001) without the formation of a SiOx interlayer between the Si (001) surface and the SrTiO3 layer because ALD is performed at lower temperatures than are typical for MBE. Thus, a combined MBE-ALD growth technique creates possible advantages in device designs that require the crystalline oxide to be in contact with the Si (001) surface. In recent work, I have demonstrated a method for integrating crystalline oxides directly on Ge by ALD. Germanium is being explored as an alternative channel material due to its higher hole and electron mobilities than Si, potentially enabling device operation at higher speed. This all-chemical growth process is expected to be scalable, is inherently less costly from a manufacturing cost of ownership, and is based on current manufacturing tool infrastructure. The impact of my research will be in continued scaling of device dimensions with novel materials that will provide faster speed and lower power consumption for microelectronic devices.Chemical Engineerin