Mechanically Flexible and Electrically Stable Organic Permeable Base Transistors

Organic transistors have attracted significant research interest in recent years due to their promises of mechanical flexibility and low-cost fabrication. Possible innovative applications include wearable electronic sensor systems, as well as mass-produced, inexpensive localization tags for logistics. However, the limited charge carrier mobility in organic semiconductor materials, contact resistance at the organic-metal interface and comparably long transistor channel lengths result low-speed organic transistors and low current densities compared with conventional inorganic transistors. The organic permeable base transistor (OPBT) is a disruptive transistor architecture that overcomes some of these drawbacks by providing a vertical transistor channel, which is much shorter than in lateral channel organic transistor devices. Consequently, it has been shown to be the fastest organic transistor to date with a transition frequency of 40 MHz, driving currents up to the kA/cm^2 regime. Nevertheless, the OPBT has not yet reached the application stage and its production has been limited to lab-scale devices deposited onto rigid glass substrates. Issues include low yield, large leakage currents, and unknown reliability of the devices. This work addresses these problems by transferring OPBTs to flexible polymer substrates and introducing a controlled and easily reproducible manufacturing technique for the crucial base oxide layer by electrochemical anodization. The anodization technique allows the creation of defined insulating layers, leading to devices with significantly reduced leakage currents and consequently very large transmission factors of 99.9996%. An investigation into the electrical stability of OPBTs shows that the devices are suitable as switching transistors in active matrix organic light emitting displays (AMOLED). In this application, the OPBT demonstrates its strengths particularly well, because fast operation and high current densities are needed. With this thesis a series of milestones on the path to commercial viability of the OPBT have been reached, making the device fit for large-scale production and integration into flexible electronic circuits, allowing it to drive the bendable organic displays of the future.:1 Introduction 2 Fundamentals 3 Experimental 4 Results – Flexible Devices 5 Results – Anodization of the Base Layer 6 Results – TEM Investigations 7 Results – Electrical Stress Measurements 8 Conclusion and OutlookDurch die Aussicht auf mechanische Flexibilität und kostengünstige Herstellung haben Organische Transistoren in den vergangenen Jahren erhebliches Forschungsinteresse geweckt. Innovative Anwendungsideen umfassen tragbare elektronische Sensorsysteme und massenproduzierte, preiswerte Ortungsetiketten für die Logistik. Leider führen die geringe Ladungsträgermobilität in organischen Halbleitermaterialien, Kontaktwiderstände am Organik-Metall-Übergang und vergleichsweise große Kanallängen der Transistoren dazu, dass organische Transistoren langsamer sind und geringere Stromdichten aufweisen als anorganische Transistoren. Der Organic Permeable Base Transistor (Organischer Transistor mit durchlässiger Basis, OPBT) stellt eine bahnbrechende Transistorarchitektur dar, die mithilfe eines vertikalen Transistorkanals einige der vorgenannten Nachteile überwindet. Dadurch ist die Kanallänge deutlich kleiner, als das bei lateralen organischen Transistorbauteilen der Fall ist. Infolgedessen kann er sich als der bisher schnellste organische Transistor mit einer Transitfrequenz von 40 MHz behaupten und Stromdichten bis in den kA/cm^2 Bereich treiben. Nichtsdestotrotz hat der OPBT bislang keine Anwendungsreife erreicht und wird derzeit nur im Labormaßstab auf starren Glassubstraten hergestellt. Hindernisse sind die geringe Produktionsausbeute, große Leckströme und die unklare Zuverlässigkeit der Bauteile. Diese Arbeit nimmt die eben genannten Herausforderungen in Angriff. Es werden OPBTs auf flexible Polymersubstrate übertragen, sowie eine kontrollierte und einfach reproduzierbare Herstellungsmethode für das wichtige Basisoxid durch elektrochemische Anodisierung eingeführt. Die Anodisierungsmethode lässt definierte Isolationsschichten entstehen, was zu stark reduzierten Leckströmen und folglich zu sehr großen Transmissionsfaktoren von 99,9996% führt. Die Untersuchung der elektrischen Stabilität von OPBTs zeigt, dass die Bauteile als Schalttransistoren in organischen Aktiv-Matrix-Displays geeignet sind. Für diese Anwendung sind die Stärken von OPBTs besonders relevant, weil kurze Schaltzeiten und hohe Stromdichten benötigt werden. Mit der vorliegenden Arbeit wird eine Reihe von Meilensteinen auf dem Weg zur kommerziellen Anwendbarkeit von OPBTs erreicht. Damit ist das Bauteil reif für die großtechnische Produktion und die Integration in flexible elektronische Schaltkreise, die die biegsamen organischen Displays der Zukunft ansteuern werden.:1 Introduction 2 Fundamentals 3 Experimental 4 Results – Flexible Devices 5 Results – Anodization of the Base Layer 6 Results – TEM Investigations 7 Results – Electrical Stress Measurements 8 Conclusion and Outloo

Oxide transistors produced by solution: Influence of annealing parameters on properties of the insulator

Solution processing of amorphous metal oxides has been lately used as an option to implement in flexible electronics allowing to reduce the associated costs and get a better performance. However the research has focused more on semiconductor layer instead of focusing on the insulator layer that is related to the stability and performance of the devices. This work aims to evaluate amorphous aluminum oxide thin films produced using different precursor solutions and processing synthesis, and the influence of different annealing parameters on properties of the insulator layer in thin film transistors (TFTs) using different semiconductors. Optimized dielectric layer was obtained for aluminum nitrate based precursor solution using urea as fuel with 0.1 M concentration for an annealing of 30 min assisted by far ultraviolet (FUV) irradiation at a lamp distance of 5 cm. These thin films were applied in gallium−indium–zinc oxide (GIZO) TFTs as dielectric showing the best results for TFTs annealed at 180 oC with FUV irradiation: a good reproducibility with an average mobility of 17.32 ± 4.15 cm2 V−1 s−1, a subthreshold slope of 0.11 ± 0.01 V dec−1 and a turn-on voltage of - 0.12 ± 0.06 V; a low operating voltage and a good stability over 9 weeks. Finally the dielectric layer was applied in solution processed indium oxide (In2O3) TFTs at low temperatures and in flexible substrates for GIZO/AlOx TFTs annealed at 200 oC with FUV irradiation. The obtained results are equivalent to the published ones and in some cases surpassing the actual state of the art

A Comparison between Solution-Based Synthesis Methods of ZrO2 Nanomaterials for Energy Storage Applications

Funding Information: This work was financed by national funds from FCT-Fundação para a Ciência e a Tecnologia, I.P., in the scope of the projects UI/BD/151292/2021 (Ph.D. research scholarship), LA/P/0037/2020, UIDP/50025/2020 and UIDB/50025/2020 of the Associate Laboratory Institute of Nanostructures, Nanomodelling and Nanofabrication-i3N, but also the 2021.03825.CEECIND. The work was also partially funded by the Nanomark collaborative project between INCM (Imprensa Nacional-Casa da Moeda) and CENIMAT/i3N. Acknowledgments also go to the EC project SYNERGY H2020-WIDESPREAD-2020-5, CSA, proposal n° 952169, EMERGE-2020-INFRAIA-2020-1, proposal n° 101008701, and to the European Community’s H2020 program under grant agreement No. 787410 (ERC-2018-AdG DIGISMART). Publisher Copyright: © 2022 by the authors.The present study is focused on the synthesis of zirconium dioxide (ZrO2) nanomaterials using the hydrothermal method assisted by microwave irradiation and solution combustion synthesis. Both synthesis techniques resulted in ZrO2 powders with a mixture of tetragonal and monoclinic phases. For microwave synthesis, a further calcination treatment at 800 °C for 15 min was carried out to produce nanopowders with a dominant monoclinic ZrO2 phase, as attested by X-ray diffraction (XRD) and Raman spectroscopy. The thermal behavior of the ZrO2 nanopowder was investigated by in situ XRD measurements. From the scanning electron microscopy (SEM) and transmission electron microscopy (TEM) images, the presence of near spherical nanoparticles was clear, and TEM confirmed the ZrO2 phases that comprised the calcinated nanopowders, which include a residual tetragonal phase. The optical properties of these ZrO2 nanopowders were assessed through photoluminescence (PL) and PL excitation (PLE) at room temperature (RT), revealing the presence of a broad emission band peaked in the visible spectral region, which suffers a redshift in its peak position, as well as intensity enhancement, after the calcination treatment. The powder resultant from the solution combustion synthesis was composed of plate-like structures with a micrometer size; however, ZrO2 nanoparticles with different shapes were also observed. Thin films were also produced by solution combustion synthesis and deposited on silicon substrates to produce energy storage devices, i.e., ZrO2 capacitors. The capacitors that were prepared from a 0.2 M zirconium nitrate-based precursor solution in 2-methoxyethanol and annealed at 350 °C exhibited an average dielectric constant (κ) of 11 ± 0.5 and low leakage current density of 3.9 ± 1.1 × 10−7 A/cm2 at 1 MV/cm. This study demonstrates the simple and cost-effective aspects of both synthesis routes to produce ZrO2 nanomaterials that can be applied to energy storage devices, such as capacitors.publishersversionpublishe

PHONON-ENERGY-COUPLING-ENHANCEMENT EFFECT AND ITS APPLICATIONS

Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication

The Application of Atomic Force Microscopy in Semiconductor Technology - Towards High-K Gate Dielectric Integration

Development of semiconductor technology over the last five decades has led to aggressive scaling down of integrated circuit (IC) device dimensions. ICs have become faster, denser and more power-efficient by continuous shrinking down of the metal-oxide-semiconductor field-effect transistor (MOSFET) size and implementation of complex integration schemes using novel materials. We are steadily approaching the physical limits of scaling and along the way more and more obstacles appear that need to be overcome in order to continue further. Traditional process control and device characterization techniques are becoming insufficient for addressing these problems. Novel techniques must be implemented for obtaining information about structural and electrical properties on materials and geometries with nanometer resolution. This is particularly relevant at the present transition from silicon dioxide gate dielectrics to ones with higher dielectric permittivity – high-K dielectrics. The present work is a contribution to this search for novel suitable analytical techniques and their implementation in semiconductor technology. It exploits extensively the high resolution imaging possibilities of atomic force microscopy (AFM) as a key support technique from the selection of prospective high-K candidates to their integration into a suitable MOSFET fabrication process. Particular attention is paid to conductive atomic force microscopy (C-AFM) which offers the possibility of mapping simultaneously topography dimensions and electrical conductivity. Initially, AFM and C-AFM are used for the development and optimization of a device isolation technology that is relevant in the context of high-K dielectrics in ultra large scale integration (ULSI) ICs – shallow trench isolation (STI). For the first time, reliable detection is obtained of the common problem related to STI – nitride erosion after the chemical planarization (CMP) step. Again with the help of C-AFM, two different techniques for planarity optimization are developed and evaluated – oxide etchback and reverse nitride masking. Next, C-AFM supports the investigation of two principally different types of prospective high-K dielectric materials. First generation dual-stack dielectrics that consist of a high-K material on top of a thin interfacial silicon dioxide layer are the easier but less effective solution. C-AFM reveals imperfections in the investigated titanium oxide – silicon dioxide stacks related to the insufficient stability of such bilayer structures. Second generation high-K dielectrics in the face of epitaxial rare-earth metal oxides possess key advantages such as higher thermal stability and the possibility for engineered interface with silicon. C-AFM investigates their properties and proves the superiority of these materials. Imperfections are observed as well that show the need for growth and processing optimizations. For the first time, charge trapping is observed on the nanoscale directly on the high-K dielectric surface. Nonuniform leakages in rare-earth metal oxides grown under insufficiently optimized conditions presumably related to grain boundaries are discovered in some samples. Based on AFM measurements, predictions are made about the expected behavior of MOS devices incorporating these materials. The compatibility of epitaxial rare-earth metal oxides with standard complementary metal-oxide-semiconductor (CMOS) processing is investigated next. Incompatibility with some steps such as for example cleaning with acid-containing solutions is determined and suitable replacement steps are chosen. Changes in film properties are determined during key steps that could indicate incompatibility of the dielectrics with the standard gate-first integration scheme. In order to determine to what extent the observed microscopic changes affect macroscopic device behavior, epitaxial dielectric layers are integrated for the first time into complete devices. Rare earth metal oxide MOSFETs are fabricated into a modified gate-first process using different gate dielectrics. C-AFM is used for process control in critical steps. Electrical evaluation of the functional devices featuring praseodymium oxide (Pr2O3), including charge pumping, reveals that at this initial stage of development the high-K gate dielectric devices suffer from degraded performance when compared to SiO2 reference devices. Imperfections such as high density of interface states, susceptibility to charge trapping and gate leakages for large area devices are observed. Neodymium oxide (Nd2O3) integration after further optimization of the gate-first process fails to produce functional devices due to substantial degradation of the gate dielectric and excessive gate leakages. The MOSFET behavior for both materials as determined by macroscopic electrical characterization results is compared to AFM predictions and they coincide very well. It is concluded that the imperfections of the gate dielectrics are at least partially a result of the integration process. Analysis is carried out and critical performance-reducing steps are identified. The gate structuring by reactive ion etch (RIE), the source/drain ion implantation and the high temperature source/drain activation anneal are responsible for the dielectric degradation to the largest extent. The inseparable link between these steps and conventional processing leads to the idea of implementing an entirely different approach for gentle integration of high-K dielectrics. Once again with the help of AFM and C-AFM, a replacement gate technology (RGT) is developed and implemented for high-K gate dielectric MOS devices in order to prove this concept. By positioning the gate dielectric growth module after the source/drain implantation and anneal and avoiding the aggressive RIE through indirect gate patterning with CMP, the integration process is adapted to the sensitive high-K materials in order to preserve their as-grown state. Electrical evaluation of devices with Gd2O3 produced using RGT proves the advantage of RGT. The first integration attempt is compared to conventional fabrication technology and there are definite improvements in terms of threshold voltage stability and interface state distribution. The first RGT high-K devices still do not exhibit the mobility and low defect density of equivalent state-of-the-art SiO2 devices but this is expected considering the 40-year-long optimization history behind silicon dioxide. Further optimization is needed for epitaxial rare-earth metal oxides as well, both in terms of growth conditions and process integration

Thin film techniques for the fabrication of nano-scale high energy density capacitors

Dielectric thin films of either TiO₂ or BaTiO₃ were sputtered in O₂/Ar plasmas on Si wafers to thicknesses ranging from approximately 25 to 200 nm with patterned Ni or Pt electrodes sputtered in Ar plasmas at thicknesses from about 20 to 250 nm to form nano-capacitors. Statistical design of experiments (DOE) was used to determine the effects of the deposition power, plasma composition, and deposition temperature on the measured electrical properties of the nano-capacitors. Additional tests to determine the effects of the dielectric and electrode thickness on the measured dielectric responses of the devices were also undertaken. Characterization was performed with a combination of direct current (DC) and alternating current (AC) testing methods including AC impedance, coercive field and leakage current versus voltage, scanning electron microscopy, transmission electron microscopy (TEM), x-ray diffraction (XRD), x-ray photoelectron spectroscopy, focused ion beam microscopy, and atomic force microscopy. The dielectric properties were found to depend on complex interactions of the process variables that could be modeled using statistical software. The permittivity was found to range from 100 to 10,000 with losses between 0.013 and 0.570. The resistance at 1 V DC varied from approximately 1.5 to 360 GΩ, and either a ferroelectric or paraelectric hysteretic response was observed for all specimens tested. Chemical analyses showed the films to be oxygen rich, while XRD and TEM data indicated the BaTiO₃ was amorphous. The electrical, chemical, and microstructural properties were found to depend on the sputtering conditions of the BaTiO₃, dielectric thickness, electrode material choice, and the electrode thickness. Collectively, the results indicated that the properties of nanometer thick dielectric and electrode materials have a significant impact on the measured electrical propertie