Optimisation of multiplier-less FIR filter design techniques

This thesis is concerned with the design of multiplier-less (ML) finite impulse response (FIR) digital filters. The use of multiplier-less digital filters results in simplified filtering structures, better throughput rates and higher speed. These characteristics are very desirable in many DSP systems. This thesis concentrates on the design of digital filters with power-of-two coefficients that result in simplified filtering structures. Two distinct classesof ML FIR filter design algorithms are developed and compared with traditional techniques. The first class is based on the sensitivity of filter coefficients to rounding to power-of-two. Novel elements include extending of the algorithm for multiple-bands filters and introducing mean square error as the sensitivity criterion. This improves the performance of the algorithm and reduces the complexity of resulting filtering structures. The second class of filter design algorithms is based on evolutionary techniques, primarily genetic algorithms. Three different algorithms based on genetic algorithm kernel are developed. They include simple genetic algorithm, knowledge-based genetic algorithm and hybrid of genetic algorithm and simulated annealing. Inclusion of the additional knowledge has been found very useful when re-designing filters or refining previous designs. Hybrid techniques are useful when exploring large, N-dimensional searching spaces. Here, the genetic algorithm is used to explore searching space rapidly, followed by fine search using simulated annealing. This approach has been found beneficial for design of high-order filters. Finally, a formula for estimation of the filter length from its specification and complementing both classes of design algorithms, has been evolved using techniques of symbolic regression and genetic programming. Although the evolved formula is very complex and not easily understandable, statistical analysis has shown that it produces more accurate results than traditional Kaiser's formula. In summary, several novel algorithms for the design of multiplier-less digital filters have been developed. They outperform traditional techniques that are used for the design of ML FIR filters and hence contributed to the knowledge in the field of ML FIR filter design

Multiplier-less low-delay FIR and IIR wavelet filter bank with SOPOT coefficients

In this paper, a new family of multiplier-less two-channel lowdelay wavelet filter banks using the PR structure in [3] and the SOPOT(sum-of-powers-of-two) representation is proposed. In particular, the functions α (z) and β (z) in the structure are chosen as nonlinear-phase FIR and IIR filters, and the design of such multiplier-less filter banks is performed using the genetic algorithm. The proposed design method is very simple to use, and is sufficiently general to construct low-delay wavelet bases with flexible length, delay, and number of zero at π (or 0) in their analysis filters. Several design examples are given to demonstrate the usefulness of the proposed method.postprin

DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.Â

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio

Multiplier-less low-delay FIR and IIR wavelet filter banks with SOPOT coefficients

In this paper, a new family of multiplier-less two-channel low-delay wavelet filter banks using the PR structure in [3] and the SOPOT(sum-of-powers-of-two) representation is proposed. In particular, the functions α(z) and β(z) in the structure are chosen as nonlinear-phase FIR and IIR filters, and the design of such multiplier-less filter banks is performed using the genetic algorithm. The proposed design method is very simple to use, and is sufficiently general to construct low-delay wavelet bases with flexible length, delay, and number of zero at π (or 0) in their analysis filters. Several design examples are given to demonstrate the usefulness of the proposed method

Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformation

This paper proposes new structures for realizing tunable 2-D fan and elliptical filters with different spectral characteristics using McClellan transformation. The 1-D prototype is a variable digital filter obtained from the interpolation of a set of desirable impulse responses and is implemented using the Farrow structure. The coefficients of the sub-filters and the transformation parameters in the Farrow structure are represented in SOPOT, which can be easily implemented as simple shift-and-add operations. Furthermore, the transformation part can be shared between the sub-filters leading to significant saving in hardware complexity. Several design examples are given to demonstrate the effectiveness and feasibility of the proposed approach.published_or_final_versio

Low-delay perfect reconstruction two-channel FIR/IIR filter banks and wavelet bases with SOPOT coefficients

IEEE International Conference on Acoustics, Speech and Signal Processing, Istanbul, Turkey, 5-9 June 2000In this paper, a new family of two-channel low-delay filter banks and wavelet bases using the PR structure in [3] with SOPOT coefficients are proposed. In particular, the functions alpha(z) and beta(z) in the structure are chosen as nonlinear-phase FIR and IIR filters, and the design of such multiplier-less filter banks is performed using the genetic algorithm. The proposed design method is very simple to use, and is sufficiently general to construct low-delay filter banks with flexible lengths, delays, and regularity. Several design examples are given to demonstrate the usefulness of the proposed method.published_or_final_versio

Low-delay perfect reconstruction two-channel FIR/IIR filter banks and wavelet bases with SOPOT coefficients

IEEE International Conference on Acoustics, Speech and Signal Processing, Istanbul, Turkey, 5-9 June 2000In this paper, a new family of two-channel low-delay filter banks and wavelet bases using the PR structure in [3] with SOPOT coefficients are proposed. In particular, the functions alpha(z) and beta(z) in the structure are chosen as nonlinear-phase FIR and IIR filters, and the design of such multiplier-less filter banks is performed using the genetic algorithm. The proposed design method is very simple to use, and is sufficiently general to construct low-delay filter banks with flexible lengths, delays, and regularity. Several design examples are given to demonstrate the usefulness of the proposed method.published_or_final_versio