Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI

科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

Ternary to binary converter design in CMOS using multiple input floating gate MOSFETS

In this work, a ternary to binary converter circuit is designed in 0.5μm n-well CMOS technology. The circuit takes two inputs corresponding to the ternary bits and gives four outputs, which are the binary equivalent bits of the ternary inputs. The ternary inputs range from (-1,-1)3 to (1,1) 3 which are decimal -4 to 4 and the four binary output bits are the sign bit (SB), most significant bit (MSB), second significant bit (SSB) and the least significant bit (LSB). The ternary inputs (-1, 0 and 1) are represented in terms of voltages of -3V, 0V and 3V. Multiple input floating gate (MIFG) MOSFETS are used in the design of ternary to binary converter. The four circuits to generate the SB, MSB, SSB and LSB outputs are designed separately and then connected together to perform the entire conversion. The MIFG MOSFET takes multiple input signals, which are the ternary inputs in this case and calculates the weighted sum of the inputs. This weighted sum of the inputs is called floating gate voltage and is given as input to the CMOS inverter. The CMOS inverter gives a high or low binary output depending on if the floating gate voltage is higher or lower than the threshold voltage of the CMOS inverter. The circuits are simulated using MOSIS BSIM level 7 model parameters. LEDIT version 13 is used for the layout and a total of 22 transistors are used in the design of the converter circuit. The floating gate of the transistor is simulated by not giving the input directly to the gate of the transistor. Instead inputs are fed to one end of the capacitors and the other end of the capacitors are tied together and given as an input to the inverter. The converter chip occupies an area of 1140 × 2090 μm2

Arithmetic logic UNIT (ALU) design using reconfigurable CMOS logic

Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented

配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

平成12年度-平成14年度科学研究費補助金(基盤研究(B)(2))研究成果報告書,課題番号.1248006

Multiple-valued content-addressable memory using metal-ferroelectric-semiconductor FETs

科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing

科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

Developing large-scale field-programmable analog arrays for rapid prototyping

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. While currently available FPAAs vary in architecture and interconnect design, they are often limited in size and flexibility. For FPAAs to be as useful and marketable as modern digital reconfigurable devices, new technologies must be explored to provide area efficient, accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed signal system. By leveraging recent advances in floating gate transistors, a new generation of FPAAs are achievable that will dramatically advance the current state of the art in terms of size, functionality, and flexibility