On Fault Diagnosis using Bayesian Networks ; A Case Study of Combinational Adders.

In this paper, we use Bayesian networks to reduce the set of vectors for the test and the diagnosis of combinational circuits. We are able to integrate any fault model (such as bit-flip and stuck-at models) and consider either single or multiple faults. We apply our method to adders and obtain a minimum set of vectors for a complete diagnosis in the case of the bit-flip model. A very good diagnosis coverage for the stuck-at fault model is found with a minimum set of test vectors and a complete diagnosis by adding few vectors

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance graceful degradation by executing in software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened. The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform it. As proof of concept a design using this idea has been developed, using the LEON3 open-source processor, synthesized on a Virtex 4 FPG

Hardware Design of Digital System with Remote-DiagnosticCapability

In this paper, a hardware design of digital systems with remote-diagnostic capability is presented. We consider a method for testing a system T(l) on a module basis with a remotely installed systems T(2). In the testing mode, we set up a system (T(l)-m,m') such that a module m of T(l) is replaced by an adapter A(1) connected to other adapter A(2) through a telephone line and the corresponding module m' of T(2) is connected to A(2). If the system (T(l)-m,m') can simulate T(1) in the absence of any faluts, then it can test m' under a self test program. The main subject of this paper is to study the conditions of the system to be testable in the above sense. At first, the remote diagnostic network based on the system in this paper, restrictions to the system configuration required to perform such a diagnosis and the operation of the diagnostic system are described. The second, the module structure to make above simulation possible is considered, representing the system configuration graphically. Finally, an example of the adapter is shown and the time consumed to diagnose is discussed. One of our results is that a sufficiently large class of synchronous digital systems with few minor conventions is testable

On Combinational Networks with Restricted Fan-Out

Fan-out-free networks of AND, OR, NOT, EXOR, and MAJORITY gates are considered. Boolean functions for which such networks exist are defined to be fan-out free. The paper solves the following problems regarding the fan-out-free networks and functions. 1) Characterization of the class of fan-out-free functions: The characterization given is constructive in the sense that if a given function is fan-out free one obtains a fan-out-free network to realize it. 2) Counting the class of fan-out-free functions: After establishing a correspondence between a fan-out-free function and a normalized network realizing it, a series of formulas are developed to count distinct normal networks for any subset of the five gates mentioned above. 3) Fault Diagnosis: Methods are developed to detect multiple faults and to locate single faults in arbitrary fan-out-free networks

Boolean Satisfiability in Electronic Design Automation

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks

A survey of an introduction to fault diagnosis algorithms

This report surveys the field of diagnosis and introduces some of the key algorithms and heuristics currently in use. Fault diagnosis is an important and a rapidly growing discipline. This is important in the design of self-repairable computers because the present diagnosis resolution of its fault-tolerant computer is limited to a functional unit or processor. Better resolution is necessary before failed units can become partially reuseable. The approach that holds the greatest promise is that of resident microdiagnostics; however, that presupposes a microprogrammable architecture for the computer being self-diagnosed. The presentation is tutorial and contains examples. An extensive bibliography of some 220 entries is included

What is the Path to Fast Fault Simulation?

Motivated by the recent advances in fast fault simulation techniques for large combinational circuits, a panel discussion has been organized for the 1988 International Test Conference. This paper is a collective account of the position statements offered by the panelists

Fault Testing for Reversible Circuits

Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test set constructions for the standard stuck-at fault model as well as the usually intractable cell-fault model. We also give a practical test set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional ATPG.Comment: 30 pages, 8 figures. to appear in IEEE Trans. on CA