Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study

The number and diversity of consumer devices are growing rapidly, alongside their target applications' memory consumption. Unfortunately, DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. Since entirely replacing DRAM with NVM in consumer devices imposes large system integration and design challenges, recent works propose extending the total main memory space available to applications by using NVM as swap space for DRAM. However, no prior work analyzes the implications of enabling a real NVM-based swap space in real consumer devices. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We extensively examine system performance and energy consumption when the NVM device is used as swap space for DRAM main memory to effectively extend the main memory capacity. For our analyses, we equip real web-based Chromebook computers with the Intel Optane SSD, which is a state-of-the-art low-latency NVM-based SSD device. We compare the performance and energy consumption of interactive workloads running on our Chromebook with NVM-based swap space, where the Intel Optane SSD capacity is used as swap space to extend main memory capacity, against two state-of-the-art systems: (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-the-art (yet slower) off-the-shelf NAND-flash-based SSD, which we use as a swap space of equivalent size as the NVM-based swap space

Data reliability and error correction for NAND Flash Memory System

NAND flash memory has been widely used for data storage due to its high density, high throughput, and low power. However, as the flash memory scales to smaller process technologies and stores more bits per cell, its reliability is decreasing. The error correction coding can be used to significantly improve the data reliability; nevertheless, the advanced ECCs such as low-density parity-check (LDPC) codes generally demand soft decisions while NAND flash memory channel provides hard-decisions only. Extracting the soft information requires the accurate characterization of flash memory channel and the effective design of coding schemes. To this end, we have presented a novel LDPC-TCM coding scheme for the Multilevel Cell (MLC) flash memories. The a posteriori TCM decoding algorithm is used in the scheme to generate soft information, which is fed to the LDPC decoder for further correction of data bits. It has been demonstrated that the proposed scheme can achieve higher error correction performance than the traditional hard-decisions based flash coding algorithms, and is feasible in the design practice. Further with the LDPC-TCM, we believe it is important to characterize the flash memory channel and investigate a method to calculate the soft decision for each bit, with the available channel outputs. We studied the various noises and interferences occurring in the memory channel and mathematically formulated the probability density function of the overall noise distribution. Based on the results we derived the final distribution for the cell threshold voltages, which can be used to instruct the calculation of soft decisions. The discoveries on the theoretical level have been demonstrated to be consistent with the real channel behaviours. The channel characterization and model provided in this dissertation can enable more design of soft-decisions based ECCs for future NAND flash memories. The data pattern processing algorithm deals with the write patterns and targets to lower the proportion of patterns that would introduce data errors. On the other hand, the voltages applied to the memory cells charges the MOSFET capacitances frequently on programming these data patterns, leading to the power problem. The high energy consumption and current spikes also cause reliability issue to the data stored in the flash memory. This dissertation proposes a write pattern formatting algorithm (WPFA) attempting to solve the two problems together. We have designed and implemented the algorithm and evaluated its performance through both the software simulations and hardware synthesis

NAND flash compiler using the SkyWater 130nm Process

NAND flash memory is commonly used for data storage, with applications in SSDs and flash drives. NAND flash research in academia can be limited by insufficient access to memory of varied sizes. This thesis discusses the design of a NAND flash memory compiler. This compiler provides researchers access to a customizable flash array. The array is built using the SkyWater Technology 130nm Process Design Kit (PDK) and SONOS flash technology. A detailed review of the implementation is included covering both the physical design of the flash array as well as the design of the compiler. The result of the compiler is able to be fabricated, as shown by an approved submission to Efabless' Multi-Project Wafer (MPW) shuttle program. The results consist of simulations that prove the functionality of the flash array

Resistive switching RAM devices based on amorphous oxide semiconductors for system on panel applications

This work reports the mask design, fabrication and characterization of memristor devices with diode like electrical behavior at pristine state. It is due to the presence of Schottky junctions between Zinc-tin-oxide (ZTO) and platinum - Indium-galliumzinc- oxide (IGZO) and molybdenum oxide for two different Metal-Insulator-Metal (MIM) configurations. The devices were exclusively produced using physical vapor deposition processes without intentional heating. Typical advanced electrical analysis of ReRAM device was performed. The Pt-ZTO-TiAu devices showed pinched hysteresis properties with large Ron=of f ratio, fast switching which can be controlled in a digital SET and analog RESET operation. However, large device-to-device variations and stability are the main issues which is due to the processing. On the other hand, the Mo-IGZO-Mo devices showed a small Ron=of f ratio and only analog operation. There was a high yield and stability. However, using DC sweep for cycling led to a charging phenomenon. Using SET/RESET pulses, the devices sustain hundreds of cycles without deterioration or movement of the resistance states, showing great resilience and retention

Signal Processing for Caching Networks and Non-volatile Memories

The recent information explosion has created a pressing need for faster and more reliable data storage and transmission schemes. This thesis focuses on two systems: caching networks and non-volatile storage systems. It proposes network protocols to improve the efficiency of information delivery and signal processing schemes to reduce errors at the physical layer as well. This thesis first investigates caching and delivery strategies for content delivery networks. Caching has been investigated as a useful technique to reduce the network burden by prefetching some contents during o˙-peak hours. Coded caching [1] proposed by Maddah-Ali and Niesen is the foundation of our algorithms and it has been shown to be a useful technique which can reduce peak traffic rates by encoding transmissions so that different users can extract different information from the same packet. Content delivery networks store information distributed across multiple servers, so as to balance the load and avoid unrecoverable losses in case of node or disk failures. On one hand, distributed storage limits the capability of combining content from different servers into a single message, causing performance losses in coded caching schemes. But, on the other hand, the inherent redundancy existing in distributed storage systems can be used to improve the performance of those schemes through parallelism. This thesis proposes a scheme combining distributed storage of the content in multiple servers and an efficient coded caching algorithm for delivery to the users. This scheme is shown to reduce the peak transmission rate below that of state-of-the-art algorithms

FPGA Application - Data Collector for TI MicroReaders Group

Import 04/07/2011Cílem této diplomové práce je realizace mikroprocesorového systému se čtyřmi asynchronními sériovými rozhraními na bázi hradlového pole, který bude zprostředkovávat sběr dat ze čteček RFID a jejich předávání pomocí sériového rozhraní. Data budou přebírána ve formátu, jaký produkuje čtečka Micro-reader RI-STU-MRD1, následně zpracována a v novém formátu posílána pro nadřazenou aplikaci. První část práce je zaměřena na použité technologie a jejich vlastnosti. Jsou zde popsány všechny důležité technologie nezbytné pro vytvoření diplomové práce. Druhá část je zaměřena na použitý hardware a také hardware, který je nutný navrhnout pomocí FPGA SmartFusion. Ve třetí časti je popsán software nezbytný k funkčnosti mikroprocesorového systému. Předposlední kapitola pojednává o testování aplikace a konečně poslední kapitola podává výsledek a přínos diplomové práce.The aim of this thesis is the realization of a microprocessor system with four asynchronous serial interfaces based on gate array, which will arrange the collection of data from RFID readers and their transmission over the serial interface. Data will be taken over in a format that produces the reader-Micro Reader RI-STU-MRD1, then they will be processed and sent to a new format for a superior application. The first part focuses on the applied technology and its properties. All the important technologies which are needed for the thesis are desribed there. The second part focuses on the hardware used and also the hardware that is required to design FPGA SmartFusion. The third section describes a software that is neccesarry for the functioning of the microprocessor system. The penultimate chapter deals with testing of application and finally the last chapter provides a result and benefit of the thesis.460 - Katedra informatikyvýborn

Improving Reliability and Performance of NAND Flash Based Storage System

High seek and rotation overhead of magnetic hard disk drive (HDD) motivates development of storage devices, which can offer good random performance. As an alternative technology, NAND flash memory demonstrates low power consumption, microsecond-order access latency and good scalability. Thanks to these advantages, NAND flash based solid state disks (SSD) show many promising applications in enterprise servers. With multi-level cell (MLC) technique, the per-bit fabrication cost is reduced and low production cost enables NAND flash memory to extend its application to the consumer electronics. Despite these advantages, limited memory endurance, long data protection latency and write amplification continue to be the major challenges in the designs of NAND flash storage systems. The limited memory endurance and long data protection latency issue derive from memory bit errors. High bit error rate (BER) severely impairs data integrity and reduces memory durance. The limited endurance is a major obstacle to apply NAND flash memory to the application with high reliability requirement. To protect data integrity, hard-decision error correction codes (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) are employed. However, the hardware cost becomes prohibitively with the increase of BER when the BCH ECC is employed to extend system lifetime. To extend system lifespan without high hardware cost, we has proposed data pattern aware (DPA) error prevention system design. DPA realizes BER reduction by minimizing the occurrence of data patterns vulnerable to high BER with simple linear feedback shift register circuits. Experimental results show that DPA can increase the system lifetime by up to 4× with marginal hardware cost. With the technology node scaling down to 2Xnm, BER increases up to 0.01. Hard-decision ECCs and DPA are no longer applicable to guarantee data integrity due to either prohibitively high hardware cost or high storage overhead. Soft-decision ECC, such as lowdensity parity check (LDPC) code, has been introduced to provide more powerful error correction capability. However, LDPC code demands extra memory sensing operations, directly leading to long read latency. To reduce LDPC code induced read latency without adverse impact on system reliability, we has proposed FlexLevel NAND flash storage system design. The FlexLevel design reduces BER by broadening the noise margin via threshold voltage (Vth) level reduction. Under relatively low BER, no extra sensing level is required and therefore read performance can be improved. To balance Vth level reduction induced capacity loss and the read speedup, the FlexLevel design identifies the data with high LDPC overhead and only performs Vth reduction to these data. Experimental results show that compared with the best existing works, the proposed design achieves up to 11% read speedup with negligible capacity loss. Write amplification is a major cause to performance and endurance degradation of the NAND flash based storage system. In the object-based NAND flash device (ONFD), write amplification partially results from onode partial update and cascading update. Onode partial update only over-writes partial data of a NAND flash page and incurs unnecessary data migration of the un-updated data. Cascading update is update to object metadata in a cascading manner due to object data update or migration. Even through only several bytes in the object metadata are updated, one or more page has to be re-written, significantly degrading write performance. To minimize write operations incurred by onode partial update and cascading update, we has proposed a Data Migration Minimizing (DMM) device design. The DMM device incorporates 1) the multi-level garbage collection technique to minimize the unnecessary data migration of onode partial update and 2) the virtual B+ tree and diff cache to reduce the write operations incurred by cascading update. The experiment results demonstrate that the DMM device can offer up to 20% write reduction compared with the best state-of-art works

Management of Intellectual Property in Supply Chain Outsourcing

Firms outsource productive tasks to different locations in order to exploit factor price differentials and gain efficiencies from specialization. However, the benefits of outsourcing come with two risks. The first problem occurs when firms share their pre-existing intellectual property (IP) such as database and trade secrets with contractors. While IP is shared to facilitate the outsourcing project, the contractor may behave opportunistically and misappropriate the IP for its own benefit. Since firms derive significant value from their IP, this can lead to severe economic damages in terms of reduced market share and brand value. The second agency problem arises due to non-contractible effort exerted by the contractor. Depending on the outsourced task, shirking can lead to higher costs and poor quality product. In this dissertation, contractual solutions are developed to mitigate these agency problems associated with outsourcing. First, several IP misappropriation cases are enumerated in the context of outsourcing. The existing literature is reviewed and the limitations are addressed in the light of these actual cases. Second, theoretical models are developed by considering two forms of IP misappropriation, depending on whether a R&D contractor emerges as a direct competitor of the principal firm, or the contractor sells the principal?s IP to a competitor. Contracts are developed to implement a ?carrot and stick? strategy, whereby firms share limited IP with their contractor and also provide incentive payments to deter shirking problem. It is shown that complementary strategies like product differentiation, task modularization, and investment in technological solutions can be useful when legal enforcement is weak. It is also demonstrated that even under the possibility of IP misappropriation; firms may gain from outsourcing if in-house inefficiency is high. However, if legal enforcement is weak, outsourcing would entail higher transaction costs. Finally, an event study is conducted to examine the effect of trade secret misappropriation on the value of Lexar. While Lexar is still outsourcing, it is explored how Lexar survived the IP misappropriation problem through product differentiation and marketing strategies