Distributed active transformer - a new power-combining andimpedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistor

Modeling of integrated inductors for RF circuit design

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnic

Design of Wireless Power Transfer and Data Telemetry System for Biomedical Applications

With the advancement of biomedical instrumentation technologies sensor based remote healthcare monitoring system is gaining more attention day by day. In this system wearable and implantable sensors are placed outside or inside of the human body. Certain sensors are needed to be placed inside the human body to acquire the information on the vital physiological phenomena such as glucose, lactate, pH, oxygen, etc. These implantable sensors have associated circuits for sensor signal processing and data transmission. Powering the circuit is always a crucial design issue. Batteries cannot be used in implantable sensors which can come in contact with the blood resulting in serious health risks. An alternate approach is to supply power wirelessly for tether-less and battery- less operation of the circuits.Inductive power transfer is the most common method of wireless power transfer to the implantable sensors. For good inductive coupling, the inductors should have high inductance and high quality factor. But the physical dimensions of the implanted inductors cannot be large due to a number of biomedical constraints. Therefore, there is a need for small sized and high inductance, high quality factor inductors for implantable sensor applications. In this work, design of a multi-spiral solenoidal printed circuit board (PCB) inductor for biomedical application is presented. The targeted frequency for power transfer is 13.56 MHz which is within the license-free industrial, scientific and medical (ISM) band. A figure of merit based optimization technique has been utilized to optimize the PCB inductors. Similar principal is applied to design on-chip inductor which could be a potential solution for further miniaturization of the implantable system. For layered human tissue the optimum frequency of power transfer is 1 GHz for smaller coil size. For this reason, design and optimization of multi-spiral solenoidal integrated inductors for 1 GHz frequency is proposed. Finally, it is demonstrated that the proposed inductors exhibit a better overall performance in comparison with the conventional inductors for biomedical applications

A Multi-objective Simulation Based Tool: Application to the Design of High Performance LC-VCOs

Part 16: Optimization Techniques in EnergyInternational audienceThe continuing size reduction of electronic devices imposes design challenges to optimize the performances of modern electronic systems, such as: wireless services, telecom and mobile computing. Fortunately, those design challenges can be overcome thanks to the development of Electronic Design Automation (EDA) tools. In the analog, mixed signal and radio-frequency (AMS/RF) domains, circuit optimization tools have demonstrated their usefulness in addressing design problems taking into account downscaling technological aspects. Recent advances in EDA have shown that the simulation-based sizing technique is a very interesting solution to the ‘complex’ modelling task in the circuit design optimization problem. In this paper we propose a multi-objective simulation-based optimization tool. A CMOS LC-VCO circuit is presented to show the viability of this tool. The tool is used to generate the Pareto front linking two conflicting objectives, namely the VCO Phase Noise and Power Consumption. The accuracy of the results is checked against HSPICE/RF simulations

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano

Compact modelling in RF CMOS technology

With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work

The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

Analysis of the impact of metal thickness and geometric parameters on the quality factor-Q in integrated spiral inductors by means of artificial bee colony technique

The goal of this present paper is to design, analysis the influence of the inductor geometrical parameters and the effect of the metal thickness on the quality factor-Q in integrated square spiral inductor using an efficient application of the artificial bee colony (ABC) algorithm. The inductors were optimized at 2.4 GHz to determinate their major geometrical dimensions (sp, w, din…) and their number of turns, for uses in radio-frequency integrated circuits (RFICs). The optimization results are validated by the simulation using an electromagnetic simulator (ADS-Momentum). Using matlab software, the study on the impact of the effect of geometrical parameters and the effect of metal thickness, on the factor of quality-Q of spiral inductors, is shown. We first reported that it is possible to improve Q-factors further by increasing the metal thickness, and in the design of inductor; a compromise must be reached between the value of w, n, sp and din to achieve the desired quality factor-Q and other electrical parameters

RF IC performance optimization by synthesizing optimum inductors

Even with optimal system design and careful choice of topology for a particular RF application, large amounts of energy are often wasted due to low-quality passives, especially inductors. Inductors have traditionally been difficult to integrate due to their inherent low quality factors and modelling complexity. Furthermore, although many different inductor configurations are available for an RF designer to explore, support for integrated inductors in electronic design automation tools and process design kits has been very limited in the past. In this chapter, a recent advance in technology-aware integrated inductor design is presented, where drawbacks of the integrated inductor design are addressed by introducing an equation-based inductor synthesis algorithm. The intelligent computation technique aims to allow RF designers to optimize integrated inductors, given the inductor center frequency dictated by the device application, and geometry constraints. This does not only lay down a foundation for system-level RF circuit performance optimization, but, because inductors are often the largest parts of an RF system, it also allows for optimal usage of chip real estate