Modeling a IF double sampling bandpass switched capacitor ΣΔ ADC with a symmetric noise transfer function for WiMAX/WLAN

4G technology aims to revolutionize private and professional communication with its ubiquity and high-speed transmission (averaging 100Mbps). WiMAX and WLAN are two of the high speed access technologies to be used in the 4G mobile communication. Apropos to their high bandwidths, oversampling converters, e.g.ΣΔ ADCs, used for these standards would entail high levels of power consumption. Double sampling technique used in ΣΔ ADCs help in reducing the power consumption, since the actual sampling rate is only half the sampling frequency required to achieve a target resolution. But for conventional modulators, with low pass noise transfer functions (NTF), this benefit is hampered by the introduction of folded noise due to the mismatch of sampling capacitances. This paper presents a novel method of designing IF bandpass switched capacitor (SC)ΣΔ modulators with symmetric NTFs. Such a bandpass NTF is formulated with its center frequency at one-fourth the effective sampling frequency. The symmetricity ensures that the folded noise is `noise-shaped' along with the quantization noise. The idea is verified with a discrete time bandpass ΣΔ modulator modeled using Simulink®, including various nonlinearities, viz. clock jitter, opampnonidealities, and capacitive mismatch effects owing to double sampling and use of a multibitquantizer. Behavioral simulations of the proposed non-ideal model for WiMAX and WLAN, with a bandwith of 10MHz and 11MHz, respectively, achieved a peak resolution greater than 10 bits for each of the standards

Desafios para a implantação de soluções de integração de aplicações empresariais em provedores de computação em nuvem

Nos últimos anos o campo de estudos conhecido como Integração de Aplicações Empresariais tem desempenhado um importante papel ao proporcionar metodologias, técnicas e ferramentas para que as empresas possam desenvolver soluções de integração, visando reutilizar suas aplicações e dar suporte às novas demandas que surgem com a evolução dos seus processos de negócio. A Computação em Nuvem é parte de uma nova realidade, na qual tanto pequenas como grandes empresas têm a sua disposição uma infraestrutura de TI de alta capacidade, a um baixo custo, na qual podem implantar e executar suas soluções de integração. O modelo de cobrança adotado pelos provedores de Computação em Nuvem se baseia na quantidade de recursos computacionais consumidos por uma solução de integração. Tais recursos podem ser conhecidos, basicamente, de duas formas distintas: a partir da execução real de uma solução de integração em um motor de orquestração, ou a partir da simulação do modelo conceitual que descreve a solução sem que a mesma tenha que ser previamente implementada. Ainda, é desejável que os provedores proporcionem modelos conceituais que descrevam detalhadamente a variabilidade de serviços e as restrições entre eles. A revisão da literatura técnica e científica evidencia que não existem metodologias, técnicas e ferramentas para estimar a demanda de recursos computacionais consumidos por soluções de integração, a partir de seus modelos conceituais. Além disso, os provedores de Computação em Nuvem não possuem ou disponibilizam os modelos conceituais dos serviços que possam ser contratados. Tais questões constituem a base para que se possa estabelecer um processo e desenvolver ferramentas de apoio a tomada de decisão para a implantação de soluções de integração de aplicações empresariais em provedores de Computação em Nuvem

Design of a Continuous-Time (CT) Sigma-Delta modulator for class D audio power amplifiers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadore

Efficient delta-sigma ADC for mobile audio applications based on a LabVIEW assisted architectural design flow

Questo lavoro di tesi è il risultato della fruttuosa collaborazione tra l’azienda multinazionale ST-Ericsson e il Dipartimento di Ingegneria dell’Informazione dell’Università di Pisa. ST-Ericsson è una delle aziende ”leader” nei mercati dei “modem“ e dei processori in banda base. Il gruppo di “mixed signal design“ nell’area di Zurigo (Svizzera) unitamente al gruppo basato a Bangalore (India) hanno, tra gli altri obbiettivi, la continua ricerca di soluzioni per migliorare l’efficienza ed il costo dei sotto-sistemi audio. Questa è stata quindi la base di lavoro per l’inizio di una collaborazione con l’accademia su tali temi. Lo studio è iniziato con una valutazione dello stato dell’arte dei “computer aided design tool” (CAD tool) per gli studi architetturali e per la validazione dei progetti dei convertitori delta-sigma sia in banda audio sia per applicazioni a larga ampiezza di banda, riscontrando una mancanza di flessibilità nell’area dei flussi per la scelta di architetture orientate al progetto. Sulla base di tali evidenze è stato sviluppato un nuovo “software” implementato in LabVIEW e finalizzato a guidare la scelta dei parametri di progetto di un convertitore analogico-digitale (ADC) delta-sigma. Tale “CAD tool” considera la minimizzazione dell’area di silicio già nella scelta dell’architettura lasciando al progettista la possibilità di implementare dei requisiti addizionali per la minimizzazione dell’area piuttosto che scegliere i parametri di progetto (coefficienti della risposta in frequenza) con il solo fine di ottenere le prestazioni desiderate. L’architettura della catena di “uplink” del processore in banda base è stata inoltre riprogettata e la funzionalità di alcuni blocchi è stata implementata nel ADC. Il controllo del guadagno, tradizionalmente effettuato da un amplificatore a guadagno variabile o “programmable gain amplifier” (PGA) attivato in corrispondenza degli attraversamenti dello zero rilevati da un “zero crossing detector” (ZCD), è stato inserito nell’anello di reazione del ADC attraverso un banco di condensatori selezionabili tramite controllo digitale. Gli effetti della commutazione del guadagno sul “dithering” e sulla traslazione del “idle-tone” sono state esaminati e sono state proposte delle soluzioni. Questo ha aperto alla possibilità di migliorare la qualità delle transizioni di guadagno attraverso un controllo a modulazione di larghezza dell’impulso o “Pulse Width Modulation” (PWM) che consente una variazione del guadagno e di conseguenza del segnale audio, molto più graduale rispetto a quanto avviene nelle soluzioni attualmente disponibili sul mercato. Infine un ADC in banda audio con area pari a 0.073 mm2 e consumo di corrente pari a 950 A da una tensione di alimentazione di 2.3 V, è stato realizzato in tecnologia CMOS 40nm. Il progetto è stato validato tramite la caratterizzazione sperimentale sia su un microchip di silicio a se’ stante contenente il solo ADC, sia sulla catena audio del processore in banda base G4860 che sta per essere adottato da Samsung per una prossima generazione di telefoni cellulari. Tra i principali obiettivi innovativi raggiunti si hanno: (i) Riduzione del 15% dell’area occupata dai condensatori commutati rispetto alle soluzioni di ADC riportati in letteratura con simili prestazioni, (ii) riduzione del 25% in area e del 30% in corrente nella catena di “uplink” audio sviluppata per un progetto GSM commerciale per mezzo dell’eliminazione sia del PGA che dello ZCD nel “front-end” audio, (iii) maggiore gradualità nel cambiamento del guadagno rispetto i dispositivi esistenti grazie ad una tecnica di controllo originale che è stata proposta per l’ottenimento di un brevetto da parte di ST-Ericsson

Circuitos digitais e mistos CMOS com aplicação em medidor de energia

The design of digital and mixed CMOS integrated circuits for energy meters is required in applications where energy measurement systems are installed with fast processing and low power consumption. The great challenge is to understand its operation and investigate topologies and/or design methodologies that allow to solve the difficulties in the design of integrated digital and mixed circuits, in order to find a good compromise between processing speed, power consumed and occupied area. In this work we present the development of new digital and mixed circuits to be used in an energy meter. The digital circuits uses a bypassing technique which avoids redundant calculations. This technique was applied in the low power multiplier, reducing its consumption by 40%. For the high-pass filter, the power consumption was reduced by 15%. And the low-pass filter had the consumption reduced by 26%. A pseudo-parallel sigma-delta modulator that was optimized at system level to attain maximum SNR using minimum capacitance values so that speed requirements of the analog blocks could be alleviated in order to reduce power consumption. The developed PSDM was verified by post-layout simulations, reaching a dynamic range of 99.8 dB for a signal bandwidth of 2 kHz, with an oversampling ratio of 128, occupying an area of 0.16 mm2 and consuming only 52.5 µW.O projeto de circuitos integrados CMOS digitais e mistos para medidores de energia se mostra necessário em aplicações nas quais se deseja diagnosticar sistemas de medição de energia elétrica com rapidez de processamento e/ou baixo consumo de potência. O grande desafio está em compreender o seu funcionamento e investigar topologias e/ou metodologias de projeto que permitam solucionar as dificuldades no projeto de circuitos integrados digitais e mistos, com o objetivo de otimizar o compromisso entre rapidez de processamento, potência consumida e área ocupada. Neste trabalho apresentamos o desenvolvimento de novos circuitos digitais e mistos para serem utilizados em um medidor de energia. Os circuitos digitais se utilizam de uma técnica de desvio que evita cálculos redundantes. Essa técnica foi aplicada no multiplicador de baixo consumo, reduzindo seu consumo em 40%. Já para o filtro passa-altas, o consumo foi reduzido em 15%. E o filtro passa-baixas teve o consumo reduzido em 26%. Um modulador sigma delta pseudo-paralelo foi otimizado ao nível do sistema para atingir o SNR máximo usando valores de capacitância mínimos para que os requisitos de velocidade dos blocos analógicos pudessem ser aliviados para reduzir o consumo de energia. O PSDM desenvolvido foi verificado por simulações pós-leiaute, atingindo uma faixa dinâmica de 99,8 dB para uma largura de banda do sinal de 2 kHz, com uma razão de sobre-amostragem de 128, ocupando uma área de 0,16 mm2 e consumindo apenas 52,5 µW

Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology

This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB OpA general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach

Integrating specification and test requirements as constraints in verification strategies for 2D and 3D analog and mixed signal designs

Analog and Mixed Signal (AMS) designs are essential components of today’s modern Integrated Circuits (ICs) used in the interface between real world signals and the digital world. They present, however, significant verification challenges. Out-of-specification failures in these systems have steadily increased, and have reached record highs in recent years. Increasing design complexity, incomplete/wrong specifications (responsible for 47% of all non functional ICs) as well as additional challenges faced when testing these systems are obvious reasons. A particular example is the escalating impact of realistic test conditions with respect to physical (interface between the device under test (DUT) and the test instruments, input-signal conditions, input impedance, etc.), functional (noise, jitter) and environmental (temperature) constraints. Unfortunately, the impact of such constraints could result in a significant loss of performance and design failure even if the design itself was flawless. Current industrial verification methodologies, each addressing specific verification challenges, have been shown to be useful for detecting and eliminating design failures. Nevertheless, decreases in first pass silicon success rates illustrate the lack of cohesive, efficient techniques to allow a predictable verification process that leads to the highest possible confidence in the correctness of AMS designs. In this PhD thesis, we propose a constraint-driven verification methodology for monitoring specifications of AMS designs. The methodology is based on the early insertion of test(s) associated with each design specification. It exploits specific constraints introduced by these planned tests as well as by the specifications themselves, as they are extracted and used during the verification process, thus reducing the risk of costly errors caused by incomplete, ambiguous or missing details in the specification documents. To fully analyze the impact of these constraints on the overall AMS design behavior, we developed a two-phase algorithm that automatically integrates them into the AMS design behavioral model and performs the specifications monitoring in a Matlab simulation environment. The effectiveness of this methodology is demonstrated for two-dimensional (2D) and three-dimensional (3D) ICs. Our results show that our approach can predict out-of-specification failures, corner cases that were not covered using previous verification methodologies. On one hand, we show that specifications satisfied without specification and test-related constraints have failed in the presence of these additional constraints. On the other hand, we show that some specifications may degrade or even cannot be verified without adding specific specification and test-related constraints

Calibrated Continuous-Time Sigma-Delta Modulators

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry

Josephson Wellenform Charakterisierung eines Sigma-Delta Analog/Digital Wandlers zur Datenerfassung in der Metrologie

A sampling system based on a 24-bits sigma-delta analog-to-digital converter (ADC) was built and characterized in order to study the feasibility of using this type of ADCs in electrical metrology. The non-linearities of the sampling system have been studied and a model for postcorrecting the measured data points established. The Hammerstein model, consisting of a static non-linear part and a linear system, was employed. A 4-th order polynomial accounts for the non-linearities of the analog electronics and the input stages of the sigma delta ADC. The linear part corresponds to the transfer function of the decimation filters internal to the ADC. The parameters for the model of the system were determined using noiseless and drift-free waveforms from a Josephson waveform synthesizer. The performance of the sampling system was verified experimentally by comparing the measured root-mean-square (rms) value of sinusoidal signals with the results from an established method. The results obtained using the post-corrected samples from the sampling system at 125 Hz agreed to within 2 μV/V with the de facto standard in metrology laboratories, which uses a high accuracy digital voltmeter. Precision measurements are limited by the decimation filters inside the ADC and can only be carried out for frequencies below 1/24-th of the equivalent sampling rate. The characterization results have shown that the non-linearities have been compensated to 5 μV/V or better and the effective resolution exceeds 20 bits, over an input range of 1 V at the equivalent sampling rate of 32 kHz. The experimental validation has proved that it is possible to measure rms values of sinusoidal signals with 1 V peak amplitudes for frequencies up to 1.3 kHz with uncertainty of 8 μV/V, significantly improving the uncertainty achievable with de facto standard which reaches 8 μV/V at 500 Hz.Ein Abtastsystem basierend auf einem 24-Bit Sigma-Delta Analog-DigitalWandler (ADC) wurde gebaut und charakterisiert, um die Möglichkeiten eines solchen ADC-Typs für Anwendungen in der elektrischen Metrologie zu untersuchen. Die Nichtlinearitäten des Abtastsystems wurden bestimmt und ein Modell für die nachträgliche Korrektur der erfassten Abtastwerte entwickelt. Dafür wurde das Hammerstein Modell verwendet, das zur Charakterisierung eines statisch, nichtlinearen Blocks gefolgt von einem linearen Teil geeignet ist. Ein Polynom vierter Ordnung wurde zur Beschreibung der statischen Nichtlinearität in der analogen Elektronik und der Eingangsstufe des Sigma-Delta ADC verwendet. Der lineare Teil des Modells umfasst die Transferfunktion des Dezimationsfilters im ADC Chip. Die Parameter für das Modell wurden mithilfe rausch- und driftloser Signale von einem Josephson Wellenform Synthesizer ermittelt. Die Leistungsfähigkeit des Abtastsystems wurde experimentell durch Effektivwertmessungen (rms) von sinusförmigen Signalen mit einem etablierten Messverfahren überprüft. Als Ergebnis wurde eine Übereinstimmung innerhalb von 2 μV/V bei 125 Hz mit dem de facto Normal der metrologischen Kalibrierlabore gefunden, das auf einem hochpräzisen Digitalvoltmeter basiert. Präzisionsmessungen haben ergeben, dass die Dezimationsfilter im ADC die maximale Frequenz auf 1/24stel der äquivalenten Abtastrate begrenzen, wenn die bestmöglichen Unsicherheiten erreicht werden sollen. Die Ergebnisse der Systemcharakterisierung haben bestätigt, dass Nichtlinearitäten auf 5 μV/V oder besser kompensiert werden. Die effektive Auflösung überschreitet 20 Bit über einen Eingangsbereich von 1 V und mit einer äquivalenten Abtastrate von 32 kHz. Die experimentelle Überprüfung hat gezeigt, dass es mit dem neuen System möglich ist, den Effektivwert sinusförmiger Signale und 1 V Amplitude für Frequenzen bis 1,3 kHz mit einer Messunsicherheit von 8 μV/V zu bestimmen, und somit die erreichbare Messunsicherheit des de facto Normals, das 8 μV/V bei 500 Hz erreicht, deutlich zu verbessern