Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Investigation of FACTS devices to improve power quality in distribution networks

Flexible AC transmission system (FACTS) technologies are power electronic solutions that improve power transmission through enhanced power transfer volume and stability, and resolve quality and reliability issues in distribution networks carrying sensitive equipment and non-linear loads. The use of FACTS in distribution systems is still in its infancy. Voltages and power ratings in distribution networks are at a level where realistic FACTS devices can be deployed. Efficient power converters and therefore loss minimisation are crucial prerequisites for deployment of FACTS devices. This thesis investigates high power semiconductor device losses in detail. Analytical closed form equations are developed for conduction loss in power devices as a function of device ratings and operating conditions. These formulae have been shown to predict losses very accurately, in line with manufacturer data. The developed formulae enable circuit designers to quickly estimate circuit losses and determine the sensitivity of those losses to device voltage and current ratings, and thus select the optimal semiconductor device for a specific application. It is shown that in the case of majority carrier devices (such as power MOSFETs), the conduction power loss (at rated current) increases linearly in relation to the varying rated current (at constant blocking voltage), but is a square root of the variable blocking voltage when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT), a similar relationship is observed for varying current, however where the blocking voltage is altered, power losses are derived as a square root with an offset (from the origin). Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel converters suited to reactive power compensation in 11kV and 33kV systems. The cascade cell converter is constructed from a series arrangement of cell modules. Two prospective structures of cascade type converters were compared as a case study: the traditional type which uses equal-sized cells in its chain, and a second with a ternary relationship between its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state conditions, with simplified models based on the switching function and using standard circuit simulators. A detailed survey of non punch through (NPT) and punch through (PT) IGBTs was completed for the purpose of designing the two cascaded converters. Results show that conduction losses are dominant in both types of converters in NPT and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to be useful in one case (27-levels in the 33kV system). The ternary-sequence converter produces lower losses in all other cases, and this is especially noticeable for the 81-level converter operating in an 11kV network

Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches. However, the power switches are conventionally characterized in terms of switching time and/or gate charge with little insight into the nonlinearities of the parasitic capacitances. This paper proposes a modelling method that can be utilized to systematically analyse the nonlinear parasitic capacitances. The existing ways of characterizing the off-state capacitance can be extended by the proposed circuit model that covers all the related states: off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize the nonlinearities of the parasitic capacitances. The equivalent circuits in different states and the evaluation equations are provided

Total Dose Simulation for High Reliability Electronics

abstract: New technologies enable the exploration of space, high-fidelity defense systems, lighting fast intercontinental communication systems as well as medical technologies that extend and improve patient lives. The basis for these technologies is high reliability electronics devised to meet stringent design goals and to operate consistently for many years deployed in the field. An on-going concern for engineers is the consequences of ionizing radiation exposure, specifically total dose effects. For many of the different applications, there is a likelihood of exposure to radiation, which can result in device degradation and potentially failure. While the total dose effects and the resulting degradation are a well-studied field and methodologies to help mitigate degradation have been developed, there is still a need for simulation techniques to help designers understand total dose effects within their design. To that end, the work presented here details simulation techniques to analyze as well as predict the total dose response of a circuit. In this dissertation the total dose effects are broken into two sub-categories, intra-device and inter-device effects in CMOS technology. Intra-device effects degrade the performance of both n-channel and p-channel transistors, while inter-device effects result in loss of device isolation. In this work, multiple case studies are presented for which total dose degradation is of concern. Through the simulation techniques, the individual device and circuit responses are modeled post-irradiation. The use of these simulation techniques by circuit designers allow predictive simulation of total dose effects, allowing focused design changes to be implemented to increase radiation tolerance of high reliability electronics.Dissertation/ThesisPh.D. Electrical Engineering 201

Benchmarking the robustness performance of SiC cascode JFETS against contemporary devices using simulations and experimental measurements

This thesis provides the first comprehensive benchmarking exercise of SiC Cascode JFETs against similarly rated SiC Planar MOSFETs, Trench MOSFETs and other devices. Experimental measurements of short circuits in single and parallel devices, single and repetitive unclamped inductive switching as well as double pulse tests are used together with finite element simulations throughout the thesis. Power device robustness measures how well a device can sustain shocks during anomalous operation. These operating conditions are high voltages that exceed the device breakdown (avalanche conduction), or simultaneous high current and voltage through the device (Short circuit conduction). The silicon Carbide (SiC) cascode JFET is an electronic switch that combines two power devices, a low voltage silicon (Si) MOSFET and a high voltage SiC JFET operating as a single switch. This configuration avoids the challenges of reduced gate oxide reliability in SiC MOSFETs, and negative turn-on Voltage for JFETs. However, the robustness of SiC cascode JFETs have not been examined as extensively as conventional devices. Hence, this thesis investigates the robustness of SiC cascode JFETs as well as the failure modes during such operation and benchmarks the performance against conventional devices. Analysis of avalanche robustness in SiC Cascode JFETs indicated a peculiar style of failure at high temperatures characterised by a soft failure (delayed turn-off, change of current slope, and dip in voltage), and an eventual catastrophic failure. This failure is different from other devices analysed which demonstrated a single catastrophic failure. The results show that the gate resistance of the SiC JFET plays a crucial role during avalanche mode conduction. Finite element simulations confirm this observation. The Short circuit (SC) robustness analysis of the SiC Cascode JFET demonstrated invariability with temperature. In contrast, benchmarked devices show a SC correlation with temperature. The short circuit operation also revealed the Cascode JFET fails with a drain source short while the gate-source junction is still functional. Also revealed is the crucial role of increasing JFET gate resistance in reducing short circuit robustness. The SC robustness is also analysed for parallel connected devices. The analysis demonstrates the parameters with the largest impact on SC current shared between paralleled devices. Variation in the embedded JFET gate resistance within the cascode JFET presents with the highest impact as confirmed by finite element simulation, while interface charges and the doping of the CSL region present with the largest impact in SiC MOSFET

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

Optimization of power MOSFET devices suitable for integrated circuits

Táto doktorská práca sa zaoberá návrhom laterálnych výkonových tranzistorov s nízkym špecifickým odporom pri zapnutom stave, vhodných pre integráciu do Integrovaných Obvodov.This doctoral thesis deals with the design of lateral power transistor with lower specific on-resistance for integration into IC.The new model of MOSFET with waffle gate pattern is there described. For first, time the conformal transformation the Schwarz-Christoffel mapping has been used for the description of nonhomogeneous current distribution in the channel area of MOSFET with waffle gate pattern. In addition base on the figure of merit definition Area Increment (AI) the topological theoretical limit of MOSFET with waffle gate pattern has been a first time defined