A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Electron beam induced deposition (EBID) of carbon interface between carbon nanotube interconnect and metal electrode

Electron Beam Induced Deposition (EBID) is an emerging additive nanomanufacturing tool which enables growth of complex 3-D parts from a variety of materials with nanoscale resolution. Fundamentals of EBID and its application to making a robust, low-contact-resistance electromechanical junction between a Multiwall Carbon Nanotube (MWNT) and a metal electrode are investigated in this thesis research. MWNTs are promising candidates for next generation electrical and electronic devices, and one of the main challenges in MWNT utilization is a high intrinsic contact resistance of the MWNT-metal electrode junction interface. EBID of an amorphous carbon interface has previously been demonstrated to simultaneously lower the electrical contact resistance and to improve mechanical characteristics of the MWNT-electrode junction. In this work, factors contributing to the EBID formation of the carbon joint between a MWNT and an electrode are systematically explored via complimentary experimental and theoretical investigations. A comprehensive dynamic model of EBID using residual hydrocarbons as a precursor molecule is developed by coupling the precursor mass transport, electron transport and scattering, and surface deposition reaction. The model is validated by comparison with experiments and is used to identify different EBID growth regimes and the growth rates and shapes of EBID deposits for each regime. In addition, the impact of MWNT properties, the electron beam impingement location and energy on the EBID-made carbon joint between the MWNT and the metal electrode is critically evaluated. Lastly, the dominant factors contributing to the overall electrical resistance of the MWNT-based electrical interconnect and relative importance of the mechanical contact area of the EBID-made carbon joint to MWNT vs. that to the metal electrode are determined using carefully designed experiments.Ph.D.Committee Chair: Dr. Andrei G. Fedorov; Committee Member: Dr. Azad Naeemi; Committee Member: Dr. Suresh Sitaraman; Committee Member: Dr. Vladimir V. Tsukruk; Committee Member: Dr. Yogendra Josh

Field-Dependent Heat Dissipation of Carbon Nanotube Electric Currents

We study heat dissipation of a multi-wall carbon nanotube (MWCNT) device fabricated from two crossed nanotubes on a SiNx substrate under the influence of a constant (DC) electric bias. By monitoring the temperature of the substrate, we observe negligible Joule heating within the nanotube lattice itself and instead heating occurs in the insulating substrate directly via a remote-scattering heating effect. Using finite element analysis, we estimate a remote heating parameter, beta, as the ratio of the power dissipated directly in the substrate to the total power applied. The extracted parameters show two distinct bias ranges; a low bias regime where about 85% of the power is dissipated directly into the substrate and a high bias regime where beta decreases, indicating the onset of traditional Joule heating within the nanotube. Analysis shows that this reduction is consistent with enhanced scattering of charge carriers by optical phonons within the nanotube. The results provide insights into heat dissipation mechanisms of Joule heated nanotube devices that are more complex than a simple heat dissipation mechanism dominated by acoustic phonons, which opens new possibilities for engineering nanoelectronics with improved thermal management

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Probing the upper limits of current flow in one-dimensional carbon conductors

We use breakdown thermometry to study carbon nanotube (CNT) devices and graphene nanoribbons (GNRs) on SiO2 substrates. Experiments and modeling find the CNT-substrate thermal coupling scales proportionally to CNT diameter. Diffuse mismatch modeling (DMM) reveals the upper limit of thermal coupling ~0.7 WK 1m 1 for the largest diameter (3-4 nm) CNTs. Similarly, we extracted the GNR thermal conductivity (TC), ~80 (130) Wm 1K 1 at 20 (600) oC across our samples, dominated by phonons, with estimated <10% electronic contribution. The TC of GNRs is an order of magnitude lower than that of micron-sized graphene on SiO2, suggesting strong roles of edge and defect scattering, and the importance of thermal dissipation in small GNR devices. We also compare the peak current density of metallic single-walled CNTs with GNRs. We find that as the “footprint” (width) between such a device and the underlying substrate decreases, heat dissipation becomes more efficient (for a given width), allowing for higher current densities. Because of their smaller dimensions and lack of edges, CNTs can carry larger current densities than GNRs, up to ~16 mA/μm for an m-SWNT with a diameter of ~0.7 nm versus ~3 mA/μm for a GNR having a width of ~15 nm. Such cur-rent densities are the highest possible in any diffusive conductor, to our knowledge. We also study semiconducting and metallic single-walled CNTs under vacuum. Sem-iconducting single-wall CNTs under high electric field stress (~10 V/µm) display a re-markable current increase due to avalanche generation of free electrons and holes. Unlike in other materials, the avalanche process in such 1D quantum wires involves access to the third subband and is insensitive to temperature, but strongly dependent on diameter ~exp( 1/d 2). Comparison with a theoretical model yields a novel approach to obtain the inelastic optical phonon emission length, λOP,ems ≈ 15d nm. We find that current in metallic single-walled CNTs does not typically saturate, unlike previous observations which suggested a maximum current of ~25 μA. In fact, at very high fields (>10 V/μm) the current continues to increase with a slope ~0.5–1 μA/V, allowing m-CNTs to reach currents well in excess of 25 μA. Subsequent modeling sug-gests that carriers tunnel from the contacts into higher subbands. This allows currents to reach ~30–35 μA, which correspond to a current density of ~9 mA/μm for diameters of ~1.2 nm

High ampacity carbon nanotube materials

This article belongs to the Special Issue The Synthesis and Applications of Carbon Nanotubes.Constant evolution of technology is leading to the improvement of electronical devices. Smaller, lighter, faster, are but a few of the properties that have been constantly improved, but these developments come hand in hand with negative downsides. In the case of miniaturization, this shortcoming is found in the inherent property of conducting materials-the limit of current density they can withstand before failure. This property, known as ampacity, is close to reaching its limits at the current scales of use, and the performances of some conductors such as gold or copper suffer severely from it. The need to find alternative conductors with higher ampacity is, therefore, an urgent need, but at the same time, one which requires simultaneous search for decreased density if it is to succeed in an ever-growing electronical world. The uses of these carbon nanotube-based materials, from airplane lightning strike protection systems to the microchip industry, will be evaluated, failure mechanisms at maximum current densities explained, limitations and difficulties in ampacity measurements with different size ranges evaluated, and future lines of research suggested. This review will therefore provide an in-depth view of the rare properties that make carbon nanotubes and their hybrids unique.This research was funded by Airbus and the Spanish Ministerio de Economia y Competitividad under grant MAT2014-57557-R

Fundamental Characterization of Low Dimensional Carbon Nanomaterials for 3D Electronics Packaging

Transistor miniaturization has over the last half century paved the way for higher value electronics every year along an exponential pace known as \u27Moore\u27s law\u27. Now, as the industry is reaching transistor features that no longer makes economic sense, this way of developing integrated circuits (ICs) is coming to its definitive end. As a solution to this problem, the industry is moving toward higher hanging fruits that can enable larger sets of functionalities and ensuring a sustained performance increase to continue delivering more cost-effective ICs every product cycle. These design strategies beyond Moore\u27s law put emphasis on 3D stacking and heterogeneous integration, which if implemented correctly, will deliver a continued development of ICs for a foreseeable future. However, this way of building semiconductor systems does bring new issues to the table as this generation of devices will place additional demands on materials to be successful. The international roadmap of devices and systems (IRDS) highlights the need for improved materials to remove bottlenecks in contemporary as well as future systems in terms of thermal dissipation and interconnect performance. For this very purpose, low dimensional carbon nanomaterials such as graphene and carbon nanotubes (CNTs) are suggested as potential candidates due to their superior thermal, electrical and mechanical properties. Therefore, a successful implementation of these materials will ensure a continued performance to cost development of IC devices.This thesis presents a research study on some fundamental materials growth and reliability aspects of low dimensional carbon based thermal interface materials (TIMs) and interconnects for electronics packaging applications. Novel TIMs and interconnects based on CNT arrays and graphene are fabricated and investigated for their thermal resistance contributions as well electrical performance. The materials are studied and optimized with the support of chemical and structural characterization. Furthermore, a reliability study was performed which found delamination issues in CNT array TIMs due to high strains from thermal expansion mismatches. This study concludes that CNT length is an important factor when designing CNT based systems and the results show that by further interface engineering, reliability can be substantially improved with maintained thermal dissipation and electrical performance. Additionally, a heat treatment study was made that enables improvement of the bulk crystallinity of the materials which will enable even better performance in future applications