IC spot-defect and fault semantics - a unified framework

A theoretical framework to model spot defects with their related faults in any IC technology is presented. The defect models are unintended geometrical variations introduced in the shape of the patterns of the IC. The transcendence of a defect is determined by the impact that it has at several levels of abstractions. This impact is called a fault. The framework is a mathematical construction which encompasses a hierarchical fault modeling that avoids irrelevant information at every level of abstraction. The framework includes consistency requirements on fault modeling which can be used to analyze the origins and reasons of malfunctions in production chip

A spot-defect to fault collapsing technique

A new technique is presented that is capable of collapsing defects to circuit faults by establishing a simple probabilistic model between them. This way of modeling supplies accurate results for ranking the failure probability of nodes and the probability of occurrence of faults. Since it is independent of the multilayer critical area extraction, the collapsing and its related applications can be done effectively in a rather short CPU time. By applying this technique, the likelihood of occurrence of faults, induced by defects, can be ranked accurately according to the conditions prevailing in the manufacturing line. The derivation of the weighted spectrums of nodes, or partial faults, can further be used for manufacturing debugging. The results of the analysis show that conventional testing methods concentrating on single stuck-at faults are insufficient and that, in particular, multiple faults need more careful treatmen

Flexible, Photopatterned, Colloidal Cdse Semiconductor Nanocrystal Integrated Circuits

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting “inks” into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with ~7 kHz bandwidths, ring oscillators with \u3c10 µs stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging

Laser : a layout sensitivity explorer : report and user's manual

As the IC pattern resolutions tend 10 become smaller the layout geometry plays a more important role in IC yield. The probability that a chip will fail is directly related to the way that the IC artwork is laid out. By examining the possible places where catastrophic defects may occur one can prevent potential faults, and thus estimate the reliability of the design. Rrealistic yield simulation tools must consider the specific layout. It is, therefore, ideal a CAE tool that automatically explores and predicts the layout reliability for real environmentai conditions prevailing in the manufacturing line. We present a system capable of interactively finding the critical areas for shorts and breaks, the sensitivity, and the yield of the IC artwork,for any range of defect sizes. The implementation is based on a simple scanline algorithm and performs only one layout extraction for any span of defect size

Application of Maxwell-Wagner polarisation in monolithic technologies

Imperial Users onl

Quantum projectors implemented with optical directional couplers in ion-exchanged glasses

Ion-exchanged glass as a platform for quantum photonics is proposed. Quantum projectors are implemented with integrated optical directional couplers fabricated by ion-exchange K+/Na+ in soda-lime glass. We consider devices composed of concatenated directional couplers which implement N-dimensional quantum projective measurements, and concomitantly the production of 1-qudit states. The fundamental units of these devices are 2 × 2 directional couplers that are experimentally studied in order to obtain, through an optical characterization, empiric relationships between fabrication and optical parameters of such couplers. Likewise, a two-dimensional quantum projector is demonstrated so that projective measurements are obtained for the states of bases X (diagonal) and Y (circular)S

Simulation Based Study of Safety Stocks under Short-Term Demand Volatility in Integrated Device Manufacturing.

© IEOM Society InternationalA problem faced by integrated device manufacturers (IDMs) relates to fluctuating demand and can be reflected in long-term demand, middle-term demand, and short-term demand fluctuations. This paper explores safety stock under short term demand fluctuations in integrated device manufacturing. The manufacturing flow of integrated circuits is conceptualized into front end and back end operations with a die bank in between. Using a model of the back-end operations of integrated circuit manufacturing, simulation experiments were conducted based on three scenarios namely a production environment of low demand volatility and high capacity reliability (Scenario A), an environment with lower capacity reliability than scenario A (Scenario B), and an environment of high demand volatility and low capacity reliability (Scenario C). Results show trade-off relation between inventory levels and delivery performance with varied degree of severity between the different scenarios studied. Generally, higher safety stock levels are required to achieve competitive delivery performance as uncertainty in demand increases and manufacturing capability reliability decreases. Back-end cycle time are also found to have detrimental impact on delivery performance as the cycle time increases. It is suggested that success of finished goods safety stock policy relies significantly on having appropriate capacity amongst others to support fluctuations

Water-gated organic transistors on polyethylene naphthalate films

Water-gated organic transistors have been successfully exploited as potentiometric transducers in a variety of sensing applications. The device response does not depend exclusively on the intrinsic properties of the active materials, as the substrate and the device interfaces play a central role. It is therefore important to fine-tune the choice of materials and layout in order to optimize the final device performance. Here, polyethylene naphthalate (PEN) has been chosen as the reference substrate to fabricate and test flexible transistors as bioelectronic transducers in liquid. PEN is a biocompatible substrate that fulfills the requirements for both bio-applications and micro-fabrication technology.Three different semiconducting or conducting polymer thin films employing pentacene, poly(3-hexylthiophene) or poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) were compared in terms of transconductance, potentiometric sensitivity and response time. The different results allow us to identify material properties crucial for the optimization of organic transistor-based transducers operating in water