An ECG-SoC with 535nW/channel lossless data compression for wearable sensors

10.1109/ASSCC.2013.6691003Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013145-14

Efficient ECG Compression and QRS Detection for E-Health Applications

Current medical screening and diagnostic procedures have shifted toward recording longer electrocardiogram (ECG) signals, which have traditionally been processed on personal computers (PCs) with high-speed multi-core processors and efficient memory processing. Battery-driven devices are now more commonly used for the same purpose and thus exploring highly efficient, low-power alternatives for local ECG signal collection and processing is essential for efficient and convenient clinical use. Several ECG compression methods have been reported in the current literature with limited discussion on the performance of the compressed and the reconstructed ECG signals in terms of the QRS complex detection accuracy. This paper proposes and evaluates different compression methods based not only on the compression ratio (CR) and percentage root-mean-square difference (PRD), but also based on the accuracy of QRS detection. In this paper, we have developed a lossy method (Methods III) and compared them to the most current lossless and lossy ECG compression methods (Method I and Method II, respectively). The proposed lossy compression method (Method III) achieves CR of 4.5×, PRD of 0.53, as well as an overall sensitivity of 99.78% and positive predictivity of 99.92% are achieved (when coupled with an existing QRS detection algorithm) on the MIT-BIH Arrhythmia database and an overall sensitivity of 99.90% and positive predictivity of 99.84% on the QT database.This work was made possible by NPRP grant #7-684-1-127 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.Scopu

An ECG-on-Chip with 535-nW/Channel Integrated Lossless Data Compressor for Wireless Sensors

This paper presents a low-power ECG recording system-on-chip (SoC) with on-chip low-complexity lossless ECG compression for data reduction in wireless/ambulatory ECG sensor devices. The chip uses a linear slope predictor for data compression, and incorporates a novel low-complexity dynamic coding-packaging scheme to frame the prediction error into fixed-length 16-bit format. The proposed technique achieves an average compression ratio of 2.25x on MIT/BIH ECG database. Implemented in a standard 0.35 um process, the compressor uses 0.565K gates/channel occupying 0.4 mm2 for four channels, and consumes 535 nW/channel at 2.4 V for ECG sampled at 512 Hz. Small size and ultra-low power consumption makes the proposed technique suitable for wearable ECG sensor applications

A Hybrid Data Compression Scheme for Power Reduction in Wireless Sensors for IoT

IEEE Transactions on Biomedical Circuits and SystemsPP991-1

VLSI Implementation of an Efficient Lossless EEG Compression Design for Wireless Body Area Network

Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 μm CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity

Power Efficient Data Compression Hardware for Wearable and Wireless Biomedical Sensing Devices

This thesis aims to verify a possible benefit lossless data compression and reduction techniques can bring to a wearable and wireless biomedical device, which is anticipated to be system power saving. A wireless transceiver is one of the main contributors to the system power of a wireless biomedical sensing device, and reducing the data transmitted by the transceiver with a minimum hardware cost can therefore help to save the power. This thesis is going to investigate the impact of the data compression and reduction on the system power of a wearable and wireless biomedical device and trying to find a proper compression technique that can achieve power saving of the device. The thesis first examines some widely used lossy and lossless data compression and reduction techniques for biomedical data, especially EEG data. Then it introduces a novel lossless biomedical data compression technique designed for this research called Log2 sub-band encoding. The thesis then moves on to the biomedical data compression evaluation of the Log2 sub-band encoding and an existing 2-stage technique consisting of the DPCM and the Huffman encoding. The next part of this thesis explores the signal classification potential of the Log2 sub-band encoding. It was found that some of the signal features extracted as a by-product during the Log2 sub-band encoding process could be used to detect certain signal events like epileptic seizures, with a proper method. The final section of the thesis focuses on the power analysis of the hardware implementation of two compression techniques referred to earlier, as well as the system power analysis. The results show that the Log2 sub-band is comparable and even superior to the 2-stage technique in terms of data compression and power performance. The system power requirement of an EEG signal recorder that has the Log2 sub-band implemented is significantly reduced

Energy-Efficient Time-Stampless Adaptive Nonuniform Sampling

Nowadays, since more and more battery-operated devices are involved in applications with continuous sensing, development of an efficient sampling mechanisms is an important issue for these applications. In this paper, we investigate power efficiency aspects of a recently proposed adaptive nonuniform sampling. This sampling scheme minimizes the energy consumption of the sampling process, which is approximately proportional to sampling rate. The main characteristics of our method are that, first, sampling times do not need to be transmitted, since the receiver can compute them by using a function of previously taken samples, and second, only innovative samples are taken from the signal of interest, reducing the sampling rate and therefore the energy consumption. We call this scheme Time-Stampless Adaptive Nonuniform Sampling (TANS). TANS can be used in several scenarios, showing promising results in terms of energy savings, and can potentially enable the development of new applications that require continuous signals sensing, such as applications related to health monitoring, location tracking and entertainment

A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.

A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the `simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um2. Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization