Efficient state reduction methods for PLA-based sequential circuits

Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems

Synthesis heuristics for large asynchronous sequential circuits

Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii

A Computer Program for Simplifying Incompletely Specified Sequential Machines Using the Paull and Unger Technique

This report presents a description of a computer program mechanized to perform the Paull and Unger process of simplifying incompletely specified sequential machines. An understanding of the process, as given in Ref. 3, is a prerequisite to the use of the techniques presented in this report. This process has specific application in the design of asynchronous digital machines and was used in the design of operational support equipment for the Mariner 1966 central computer and sequencer. A typical sequential machine design problem is presented to show where the Paull and Unger process has application. A description of the Paull and Unger process together with a description of the computer algorithms used to develop the program mechanization are presented. Several examples are used to clarify the Paull and Unger process and the computer algorithms. Program flow diagrams, program listings, and a program user operating procedures are included as appendixes

State assignment for sequential circuits using multi-objective genetic algorithm

In this study, a new approach using a multi-objective genetic algorithm (MOGA) is proposed to determine the optimal state assignment with less area and power dissipations for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity. The MOGA employs a Pareto ranking scheme and produces a set of state assignments, which are optimal in both objectives. The ESPRESSO tool is used to optimise the combinational parts of the sequential circuits. Experimental results are given using a personal computer with an Intel CPU of 2.4 GHz and 2 GB RAM. The algorithm is implemented using C++ and fully tested with benchmark examples. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recent published research

A Simplification Heuristic For Large Flow Tables

Flow tables specifying large asynchronous sequential circuits often contain more internal states than are required to specify desired circuit behavior. Known minimization techniques appear unsuited for reduction of such large (rows X columns \u3e 250) flow tables, because of excessive computation and intermediate data requirements for problems of this size. The algorithm described here is intended to rapidly produce a simplified-but in general non-minimal-flow table. It is most economical when applied to extremely large tables and was devised primarily for automated design applications. The procedure has been programmed in PL/1 and has been incorporated into an asynchronous sequential circuit design automation system developed at the University of Missouri-Rolla. Typical flow table simplification times obtained using the program are cited. In one test re-duction of a 217 row x 8 column table to 39x8 required about 2.6 minutes (the minimum table in this case was known to be 23x8)

SPECIFICATION AND REALISATION OF LOGIC CONTROL PROCEDURES ON THE BASIS OF PRESCRIBED INPUT-OUTPUT CHANGES

In this report, a method is outlined for handling the logic control procedures both in the specification level and on the hardware implementation level of the design. The heuristic and intuitive character of constructing the flow chart and defining the states has been reduced to a large extent. This method may result in several kinds of uniform hardware structures for either synchronous or asynchronous control units initially specified only by input-output sequences. Introducing differential mappings for the description of sequential operation, the prescribed sequences for input and output changes can be considered as the initial specification of a control unit. This specification yields a so-called B : K table and aB: K graph as representation of the required operation. The definition of the states is made by interpreting the compatibility relation between the prescribed output changes. . The procedure of the state definition results in the B: K : A set or graph which corresponds to the minimised flow table obtained from the state reduction of incompletely specified sequential circuits. The properties of the canonical B : K set and graph always ensure the existence of an optimal cover. If the fixed hardware structure contains flip-flops for storing the output combination, then the influence of these flip-flops on the state reduction are automatically taken into consideration by the method outlined in the report. Also, by the introduction of an optimal cover for the identifying functions related to the output changes, the logical expressions for the realisation of the hardware can be simplified. The specification and description method, outlined in this report, has the advantage of defining the prescribed sequences of input and output changes in separate fragments. Applying the prescribed input section changes. these separate fragments can be joined together and the B : K set can be calculated systematically. In this way, the specification for the synthesis procedure may become more rigorous than it was initially. However, it is not necessary to form a coherent specification by intuition

Automation In The Design Of Asynchronous Sequential Circuits

Sequential switching circuits are commonly classified as being either synchronous or asynchronous. Clock pulses synchronize the operations of the synchronous circuit. The operation of an asynchronous circuit is usually assumed to be independent of such clocks. The operating speed of an asynchronous circuit is thus limited only by basic device speed. One disadvantage of asynchronous circuit design has been the complexity of the synthesis procedures for large circuits