A digital tuning scheme for digitally programmable integrated continuous-time filters and techniques for high-precision monolithic linear circuit design and implementation

Multiple topics which all focus on precision monolithic circuit design but beyond this are not directly related to each other are presented. The first topic is a digital tuning scheme for digitally programmable integrated continuous-time filters (4), (8) - (10). Emphasis of this research is on development of a more general tuning scheme which can be applicable to various filter functions as well as high-frequency applications. The tuning scheme consists of two phases: system identification and adjustment. Various continuous-time filter identification methods including time-domain and frequency-domain approaches are investigated, and a filter adjustment algorithm is presented. Potential of high accuracy of the proposed tuning scheme and successful applicability to high-frequency filters with versatile functions have been demonstrated through simulations and experiments;Four other topics are separately presented. First, nonidealities associated with high-precision amplifiers (5), (7) are discussed. Special emphasis is given on analysis of statistical characteristics of random CMRR and offset of CMOS op-amps which can help estimating yield of high-volume production and help engineers design for a given yield. Next, an automatic offset compensation scheme for CMOS op-amps with ping-pong control (2), (6) is presented. A very low-voltage circuit design technique using floating gate MOSFETs (3) is introduced. Finally, an accurate and matching-free threshold voltage extraction scheme using a ratio-independent SC amplifier and a dynamic current mirror (1) is discussed

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV

Switched-compensation technique in switched-capacitor circuits for achieving fast settling performance

Resolving stability issue is one of the major challenges in designing a perfect op-amp, the most widely used analog circuit block. Many compensation techniques have been proposed to improve the stability performance of op amps, but virtually all these techniques were developed for continuous-time applications and subsequently applied to discrete-time applications (e.g., switched-capacitor circuits). Since the early 1980s, an increasing number of op-amps have been used in switched-capacitor circuits with no special compensation method applied. Consequently, there remains a need to explore the possibility of designing a unique compensation method specifically for switched-capacitor use. A new switched-compensation technique (SCT) is proposed for switched-capacitor circuit applications in which high speed is a critical index of performance. In general, designers must deal with trade-offs among accuracy, speed, and power dissipation. SCT avoids traditional approaches of designing high-speed, high-gain operational amplifiers that are in many cases technology-limited. Instead, it modifies the switched-capacitor circuit structure to use the under-damped response of the system, usually regarded as a drawback. SCT is introduced as a novel solution for achieving fast settling performance and lower quiescent power dissipation while guaranteeing almost equivalent accuracy. SCT can be easily implemented in flip-around switched-capacitor amplifier circuits. This paper explains SCT principle and implementation applied to multiplying-digital-to-analog converters (MDACs) as a proof of concept. Simulation results based on an IBM 0.13um CMOS process are presented. Compared with a conventional switched-capacitor amplifier, a SCT-based implementation reduces the quiescent power consumption by half and settling time within 1% error by 60%

Delta-Sigma Modulator based Compact Sensor Signal Acquisition Front-end System

The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of $\Delta\Sigma$M. The DDA also provides balanced high input impedance for signal from sensors. Further, programmable input amplification is obtained by adjustment of $\Delta\Sigma$M feedback voltage. Implementation of other functionalities, such as filtering and digitization have also been incorporated. At circuit level, a difference of transconductance of DDA input pairs has been proposed to reduce the effect of input resistor thermal noise of front-end R-C integrator of the $\Delta\Sigma$M. Besides, chopping has been used for minimizing effect of Flicker noise. The resulting architecture is an aggregation of functions of entire signal acquisition system within the single block of $\Delta\Sigma$M, and is useful for a multitude of dc-to-medium frequency sensing and similar applications that require high precision at reduced size and power. An implementation of this in 0.18-$\mu$m CMOS process has been presented, yielding a simulated peak signal-to-noise ratio of 80 dB and dynamic range of 109dBFS in an input signal band of 1 kHz while consuming 100 $\mu$W of power; with the measured signal-to-noise ratio being lower by about 9 dB.Comment: 13 pages, 16 figure

Model of Switched-Capacitor Programmable Voltage Reference: Optimization for Ultra Low-Power Applications

This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVREF). This PVREF topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. Circuit optimization is carried out with MATLAB and permits SC-PVREF to achieve current consumptions of tens of nanoampere, suitable for ultra low-power applications