690 research outputs found
Effective network grid synthesis and optimization for high performance very large scale integration system design
制度:新 ; 文部省報告番号:甲2642号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新480
Performance and power optimization in VLSI physical design
As VLSI technology enters the nanoscale regime, a great amount of efforts have
been made to reduce interconnect delay. Among them, buffer insertion stands out
as an effective technique for timing optimization. A dramatic rise in on-chip buffer
density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates
are buffers.
In this thesis, three buffer insertion algorithms are presented for the procedure
of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under
the dynamic programming framework and runs in provably linear time for multiple
buffer types due to two novel techniques: restrictive cost bucketing and efficient delay
update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution
quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter
time and the buffered tree has better timing.
The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce
via variation and signal distortion in twisted differential line. In addition, a new
buffer insertion technique is proposed to synchronize the transmitted signals, thus
further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new
approaches. In contrast, only a 100MHz signal can be reliably transmitted using a
single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45%
as witnessed in our simulation.
The fourth chapter proposes a buffer insertion and gate sizing algorithm for
million plus gates. The algorithm takes a combinational circuit as input instead of
individual nets and greatly reduces the buffer and gate cost of the entire circuit.
The algorithm has two main features: 1) A circuit partition technique based on the
criticality of the primary inputs, which provides the scalability for the algorithm, and
2) A linear programming formulation of non-linear delay versus cost tradeoff, which
formulates the simultaneous buffer insertion and gate sizing into linear programming
problem. Experimental results on ISCAS85 circuits show that even without the circuit
partition technique, the new algorithm achieves 17X speedup compared with path
based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9%
gate cost, 5.8% total cost and results in less circuit delay
Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks
Multilayered artificial neural networks (ANN) have found widespread utility
in classification and recognition applications. The scale and complexity of
such networks together with the inadequacies of general purpose computing
platforms have led to a significant interest in the development of efficient
hardware implementations. In this work, we focus on designing energy efficient
on-chip storage for the synaptic weights. In order to minimize the power
consumption of typical digital CMOS implementations of such large-scale
networks, the digital neurons could be operated reliably at scaled voltages by
reducing the clock frequency. On the contrary, the on-chip synaptic storage
designed using a conventional 6T SRAM is susceptible to bitcell failures at
reduced voltages. However, the intrinsic error resiliency of NNs to small
synaptic weight perturbations enables us to scale the operating voltage of the
6TSRAM. Our analysis on a widely used digit recognition dataset indicates that
the voltage can be scaled by 200mV from the nominal operating voltage (950mV)
for practically no loss (less than 0.5%) in accuracy (22nm predictive
technology). Scaling beyond that causes substantial performance degradation
owing to increased probability of failures in the MSBs of the synaptic weights.
We, therefore propose a significance driven hybrid 8T-6T SRAM, wherein the
sensitive MSBs are stored in 8T bitcells that are robust at scaled voltages due
to decoupled read and write paths. In an effort to further minimize the area
penalty, we present a synaptic-sensitivity driven hybrid memory architecture
consisting of multiple 8T-6T SRAM banks. Our circuit to system-level simulation
framework shows that the proposed synaptic-sensitivity driven architecture
provides a 30.91% reduction in the memory access power with a 10.41% area
overhead, for less than 1% loss in the classification accuracy.Comment: Accepted in Design, Automation and Test in Europe 2016 conference
(DATE-2016
Elasticity and Petri nets
Digital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with communication handshakes (asynchronous version) or by augmenting the clock with a synchronous version of a handshake (synchronous version). Time elastic systems can tolerate static and dynamic changes in delays (asynchronous case) or latencies (synchronous case) of operations that can be used for modularity, ease of reuse and better power-delay trade-off. This paper describes methods for the modeling, performance analysis and optimization of elastic systems using Marked Graphs and their extensions capable of describing behavior with early evaluation. The paper uses synchronous elastic systems (aka latency-tolerant systems) for illustrating the use of Petri nets, however, most of the methods can be applied without changes (except changing the delay model associated with events of the system) to asynchronous elastic systems.Peer ReviewedPostprint (author's final draft
Enhancing Power Efficient Design Techniques in Deep Submicron Era
Excessive power dissipation has been one of the major bottlenecks for design and
manufacture in the past couple of decades. Power efficient design has become
more and more challenging when technology scales down to the deep submicron era
that features the dominance of leakage, the manufacture variation, the on-chip
temperature variation and higher reliability requirements, among others. Most of the computer aided design (CAD) tools and algorithms currently used in industry
were developed in the pre deep submicron era and did not consider the new features explicitly and adequately.
Recent research advances in deep submicron design, such as the mechanisms of leakage, the source and characterization of manufacture variation, the cause and
models of on-chip temperature variation, provide us the opportunity to incorporate these important issues in power efficient design. We explore this opportunity in this dissertation by demonstrating that significant power reduction can be achieved with only minor modification to the existing CAD tools and algorithms.
First, we consider peak current, which has become critical for circuit's reliability in deep submicron design. Traditional low power design techniques focus on
the reduction of average power. We propose to reduce peak current while keeping the overhead on average power as small as possible. Second, dual Vt technique and gate sizing have been used simultaneously for leakage savings. However, this approach becomes less effective in deep submicron design. We propose to use the newly developed process-induced mechanical stress to enhance its performance.
Finally, in deep submicron design, the impact of on-chip temperature variation on leakage and performance becomes more and more significant. We propose a temperature-aware dual Vt approach to alleviate hot spots and achieve further leakage reduction. We also consider this leakage-temperature dependency in the dynamic voltage scaling approach and discover that a commonly accepted result is incorrect for the current technology.
We conduct extensive experiments with popular design benchmarks, using the latest industry CAD tools and design libraries. The results show that our proposed enhancements are promising in power saving and are practical to solve the low power design challenges in deep submicron era
Designing a Ring Oscillator Using Nanotechnology through Cadence Virtuoso
This paper presents the design and simulation of a ring oscillator using nanotechnology and the Cadence Virtuoso platform. As feature sizes continue to shrink, new design methodologies are required to account for quantum effects that become prominent at the nanoscale. This paper utilizes predictive technology models for a 45nm process to design a three-stage ring oscillator with minimum channel lengths. The ring oscillator design is optimized through careful selection of transistor characteristics and layout considerations. Post-layout simulations demonstrate functionality with oscillation frequency and phase noise matching expected theoretical values. The completed design provides a demonstration of a basic analog circuit block implemented with nanoscale technology.
 
A Multiple-objective ILP based Global Routing Approach for VLSI ASIC Design
A VLSI chip can today contain hundreds of millions transistors and is expected to
contain more than 1 billion transistors in the next decade.
In order to handle this rapid growth in integration technology,
the design procedure is therefore divided into a sequence of design
steps. Circuit layout is the design step in which a physical
realization of a circuit is obtained from its functional description.
Global routing is one of the key subproblems of the circuit layout
which involves finding an approximate path for the wires connecting the
elements of the circuit without violating resource constraints.
The global routing problem is NP-hard, therefore, heuristics capable of
producing high quality routes with little computational effort are required
as we move into the Deep Sub-Micron (DSM) regime.
In this thesis, different approaches for global routing problem are first
reviewed. The advantages and disadvantages of these approaches are also summarized.
According to this literature review, several mathematical programming based global
routing models are fully investigated. Quality of solution obtained by
these models are then compared with traditional Maze routing technique.
The experimental results show that the proposed model can optimize several global routing
objectives simultaneously and effectively. Also, it is easy to incorporate new
objectives into the proposed global routing model.
To speedup the computation time of the proposed ILP based global router, several
hierarchical methods are combined with the flat ILP based global routing
approach. The experimental results indicate that the bottom-up global routing
method can reduce the computation time effectively with a slight increase of maximum
routing density.
In addition to wire area, routability, and vias, performance and low power
are also important goals in global routing, especially in deep submicron designs.
Previous efforts that focused on power optimization for global routing
are hindered by excessively long run times or the routing of a subset of the
nets. Accordingly, a power efficient multi-pin global routing
technique (PIRT) is proposed in this thesis.
This integer linear programming based techniques strives to find a power
efficient global routing solution.
The results indicate that an average power savings as high as 32\% for the
130-nm technology can be achieved with no impact on the maximum chip frequency
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