A VLSI chip can today contain hundreds of millions transistors and is expected to
contain more than 1 billion transistors in the next decade.
In order to handle this rapid growth in integration technology,
the design procedure is therefore divided into a sequence of design
steps. Circuit layout is the design step in which a physical
realization of a circuit is obtained from its functional description.
Global routing is one of the key subproblems of the circuit layout
which involves finding an approximate path for the wires connecting the
elements of the circuit without violating resource constraints.
The global routing problem is NP-hard, therefore, heuristics capable of
producing high quality routes with little computational effort are required
as we move into the Deep Sub-Micron (DSM) regime.
In this thesis, different approaches for global routing problem are first
reviewed. The advantages and disadvantages of these approaches are also summarized.
According to this literature review, several mathematical programming based global
routing models are fully investigated. Quality of solution obtained by
these models are then compared with traditional Maze routing technique.
The experimental results show that the proposed model can optimize several global routing
objectives simultaneously and effectively. Also, it is easy to incorporate new
objectives into the proposed global routing model.
To speedup the computation time of the proposed ILP based global router, several
hierarchical methods are combined with the flat ILP based global routing
approach. The experimental results indicate that the bottom-up global routing
method can reduce the computation time effectively with a slight increase of maximum
routing density.
In addition to wire area, routability, and vias, performance and low power
are also important goals in global routing, especially in deep submicron designs.
Previous efforts that focused on power optimization for global routing
are hindered by excessively long run times or the routing of a subset of the
nets. Accordingly, a power efficient multi-pin global routing
technique (PIRT) is proposed in this thesis.
This integer linear programming based techniques strives to find a power
efficient global routing solution.
The results indicate that an average power savings as high as 32\% for the
130-nm technology can be achieved with no impact on the maximum chip frequency
