The development of an airborne instrumentation computer system for flight test

Instrumentation interfacing frequently requires the linking of intelligent systems together, as well as requiring the link itself to be intelligent. The airborne instrumentation computer system (AICS) was developed to address this requirement. Its small size, approximately 254 by 133 by 140 mm (10 by 51/4 by 51/2 in), standard bus, and modular board configuration give it the ability to solve instrumentation interfacing and computation problems without forcing a redesign of the entire unit. This system has been used on the F-15 aircraft digital electronic engine control (DEEC) and its follow on engine model derivative (EMD) project and in an OV-1C Mohawk aircraft stall speed warning system. The AICS is presently undergoing configuration for use on an F-104 pace aircraft and on the advanced fighter technology integration (AFTI) F-111 aircraft

Hierarchical stack filtering : a bitplane-based algorithm for massively parallel processors

With the development of novel parallel architectures for image processing, the implementation of well-known image operators needs to be reformulated to take advantage of the so-called massive parallelism. In this work, we propose a general algorithm that implements a large class of nonlinear filters, called stack filters, with a 2D-array processor. The proposed method consists of decomposing an image into bitplanes with the bitwise decomposition, and then process every bitplane hierarchically. The filtered image is reconstructed by simply stacking the filtered bitplanes according to their order of significance. Owing to its hierarchical structure, our algorithm allows us to trade-off between image quality and processing time, and to significantly reduce the computation time of low-entropy images. Also, experimental tests show that the processing time of our method is substantially lower than that of classical methods when using large structuring elements. All these features are of interest to a variety of real-time applications based on morphological operations such as video segmentation and video enhancement

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

FPGA Implementation of an Adaptive Noise Canceller for Robust Speech Enhancement Interfaces

This paper describes the design and implementation results of an adaptive Noise Canceller useful for the construction of Robust Speech Enhancement Interfaces. The algorithm being used has very good performance for real time applications. Its main disadvantage is the requirement of calculating several operations of division, having a high computational cost. Besides that, the accuracy of the algorithm is critical in fixed-point representation due to the wide range of the upper and lower bounds of the variables implied in the algorithm. To solve this problem, the accuracy is studied and according to the results obtained a specific word-length has been adopted for each variable. The algorithm has been implemented for Altera and Xilinx FPGAs using high level synthesis tools. The results for a fixed format of 40 bits for all the variables and for a specific word-length for each variable are analyzed and discussed

Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models

Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. Any device that can reduce the load on, for example, a PC’s processor, is advantageous. Hence we present FPGA implementations of the decoder based alternately on discrete and continuous hidden Markov models (HMMs) representing monophones, and demonstrate that the discrete version can process speech nearly 5,000 times real time, using just 12% of the slices of a Xilinx Virtex XCV1000, but with a lower recognition rate than the continuous implementation, which is 75 times faster than real time, and occupies 45% of the same device

Overview of Parallel Platforms for Common High Performance Computing

The paper deals with various parallel platforms used for high performance computing in the signal processing domain. More precisely, the methods exploiting the multicores central processing units such as message passing interface and OpenMP are taken into account. The properties of the programming methods are experimentally proved in the application of a fast Fourier transform and a discrete cosine transform and they are compared with the possibilities of MATLAB's built-in functions and Texas Instruments digital signal processors with very long instruction word architectures. New FFT and DCT implementations were proposed and tested. The implementation phase was compared with CPU based computing methods and with possibilities of the Texas Instruments digital signal processing library on C6747 floating-point DSPs. The optimal combination of computing methods in the signal processing domain and new, fast routines' implementation is proposed as well

An automated stall-speed warning system

The development and testing of a stall-speed warning system for the OV-1C was examined. NASA designed and built an automated stall-speed warning system which presents both airspeed and stall speed to the pilot. The airspeed and stall speed are computed in real time by monitoring the basic aerodynamic parameters (dynamic pressure, horizontal and vertical accelerations, and pressure altitude) and other parameters (elevator and flap positions, engine torques, and fuel flow). In addition, an aural warning at predetermined stall margins is presented to the pilot through a voice synthesizer. Once the system was designed and installed in the aircraft, a flight-test program of less than 20 hrs was anticipated to determine the stall-speed software coefficients. These coefficients would then be inserted in the system's software and then test flown over a period of about 10 hr for the purpose of evaluation

Sentient Networks

In this paper we consider the question whether a distributed network of sensors and data processors can form "perceptions" based on the sensory data. Because sensory data can have exponentially many explanations, the use of a central data processor to analyze the outputs from a large ensemble of sensors will in general introduce unacceptable latencies for responding to dangerous situations. A better idea is to use a distributed "Helmholtz machine" architecture in which the collective state of the network as a whole provides an explanation for the sensory data.Comment: PostScript, 14 page