Thermo-mechanical stress of bonded wires used in high power modules with alternating and direct current modes

Today, power electronic reliability is a main subject of interest for many companies and laboratories. The main process leading to the IGBT failure is the cycling thermal stress. Indeed the current flow induce local heating and then mechanical stress. This paper deals with electro thermal stress under steady and transient current states. The main objective is to test bonded wires with active current cycle. Consequently, the thermo mechanical stress is obtained. A numerical 3D finite element model is presented and some experimental results are given. Indeed an infrared system monitors the temperature dispatching from an experimental test bench under active current cycle. The overall study is a first step before a global simulation (electrical thermal-mechanical) in order to optimize some geometric parameters of the packaging

A novel method for fatigue testing of MEMS devices containing movable elements

In this paper we present an electronic circuit for position or capacitance estimation of MEMS electrostatic actuators based on a switched capacitor technique. The circuit uses a capacitive divider configuration composed by a fixed capacitor and the variable capacitance of the electrostatic actuator for generating a signal that is a function of the input voltage and capacitive ratio. The proposed circuit can be used to actuate and to sense position of an electrostatic MEMS actuator without extra sensing elements. This approach is compatible with the requirements of most analog feedback systems and the circuit topology of pulsed digital oscillators (PDO).Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

Optimizing construction of scheduled data flow graph for on-line testability

The objective of this work is to develop a new methodology for behavioural synthesis using a flow of synthesis, better suited to the scheduling of independent calculations and non-concurrent online testing. The traditional behavioural synthesis process can be defined as the compilation of an algorithmic specification into an architecture composed of a data path and a controller. This stream of synthesis generally involves scheduling, resource allocation, generation of the data path and controller synthesis. Experiments showed that optimization started at the high level synthesis improves the performance of the result, yet the current tools do not offer synthesis optimizations that from the RTL level. This justifies the development of an optimization methodology which takes effect from the behavioural specification and accompanying the synthesis process in its various stages. In this paper we propose the use of algebraic properties (commutativity, associativity and distributivity) to transform readable mathematical formulas of algorithmic specifications into mathematical formulas evaluated efficiently. This will effectively reduce the execution time of scheduling calculations and increase the possibilities of testability

Thick-Film and LTCC Passive Components for High-Temperature Electronics

At this very moment an increasing interest in the field of high-temperature electronics is observed. This is a result of development in the area of wide-band semiconductors’ engineering but this also generates needs for passives with appropriate characteristics. This paper presents fabrication as well as electrical and stability properties of passive components (resistors, capacitors, inductors) made in thick-film or Low-Temperature Co-fired Ceramics (LTCC) technologies fulfilling demands of high-temperature electronics. Passives with standard dimensions usually are prepared by screen-printing whereas combination of standard screen-printing with photolithography or laser shaping are recommenced for fabrication of micropassives. Attainment of proper characteristics versus temperature as well as satisfactory long-term high-temperature stability of micropassives is more difficult than for structures with typical dimensions for thick-film and LTCC technologies because of increase of interfacial processes’ importance. However it is shown that proper selection of thick-film inks together with proper deposition method permit to prepare thick-film micropassives (microresistors, air-cored microinductors and interdigital microcapacitors) suitable for the temperature range between 150°C and 400°C

Optimal edge termination for high oxide reliability aiming 10kV SiC n-IGBTs

The edge termination design strongly affects the ability of a power device to support the desired voltage and its reliable operation. In this paper we present three appropriate termination designs for 10kV n-IGBTs which achieve the desired blocking requirement without the need for deep and expensive implantations. Thus, they improve the ability to fabricate, minimise the cost and reduce the lattice damage due to the high implantation energy. The edge terminations presented are optimised both for achieving the widest immunity to dopant activation and to minimise the electric field at the oxide. Thus, they ensure the long-term reliability of the device. This work has shown that the optimum design for blocking voltage and widest dose window does not necessarily give the best design for reliability. Further, it has been shown that Hybrid Junction Termination Extension structure with Space Modulated Floating Field Rings can give the best result of very high termination efficiency, as high as 99%, the widest doping variation immunity and the lowest electric field in the oxide

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated