Highly Automated Formal Verification of Arithmetic Circuits

This dissertation investigates the problems of two distinctive formal verification techniques for verifying large scale multiplier circuits and proposes two approaches to overcome some of these problems. The first technique is equivalence checking based on recurrence relations, while the second one is the symbolic computation technique which is based on the theory of Gröbner bases. This investigation demonstrates that approaches based on symbolic computation have better scalability and more robustness than state-of-the-art equivalence checking techniques for verification of arithmetic circuits. According to this conclusion, the thesis leverages the symbolic computation technique to verify floating-point designs. It proposes a new algebraic equivalence checking, in contrast to classical combinational equivalence checking, the proposed technique is capable of checking the equivalence of two circuits which have different architectures of arithmetic units as well as control logic parts, e.g., floating-point multipliers

Experiments in Automating Hardware Verification using Inductive Proof Planning

We present a new approach to automating the verification of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using specifications of their behaviour. Given a verification problem, a planner uses the method database to build automatically a specialised tactic to solve the given problem. User interaction is limited to specifying circuits and their properties and, in some cases, suggesting lemmas. We have implemented our work in an extension of the Clam proof planning system. We report on this and its application to verifying a variety of combinational and synchronous sequential circuits including a parameterised multiplier design and a simple computer microprocessor

Development and Validation of a Spike Detection and Classification Algorithm Aimed at Implementation on Hardware Devices

Neurons cultured in vitro on MicroElectrode Array (MEA) devices connect to each other, forming a network. To study electrophysiological activity and long term plasticity effects, long period recording and spike sorter methods are needed. Therefore, on-line and real time analysis, optimization of memory use and data transmission rate improvement become necessary. We developed an algorithm for amplitude-threshold spikes detection, whose performances were verified with (a) statistical analysis on both simulated and real signal and (b) Big O Notation. Moreover, we developed a PCA-hierarchical classifier, evaluated on simulated and real signal. Finally we proposed a spike detection hardware design on FPGA, whose feasibility was verified in terms of CLBs number, memory occupation and temporal requirements; once realized, it will be able to execute on-line detection and real time waveform analysis, reducing data storage problems

On applications of dependent types to parameterised digital signal processing circuits

We explore the use of dependent types to address the disparity between the theory and the practical hardware description of DSP circuits. After discussing an approach to modeling synchronous circuit behaviour in Idris (a pure functional language with dependent types), two DSP case studies are introduced — an FIR filter with optimal wordlengths and a CIC decimator with register pruning. Both of these scenarios prove difficult to describe in a parameterised fashion using traditional HDLs and, as such, many implementations rely on ad hoc circuit generators which are challenging to test and evaluate. This work demonstrates that such circuits are readily described in an environment with dependent types. Dependent types can also encode various contracts between the IP designer and its user. These contracts are automatically verified by the Idris type checker before compilation, precluding many common mistakes in IP development and evaluation

Deterministic, Efficient Variation of Circuit Components to Improve Resistance to Reverse Engineering

This research proposes two alternative methods for generating semantically equivalent circuit variants which leave the circuit\u27s internal structure pseudo-randomly determined. Component fusion deterministically selects subcircuits using a component identification algorithm and replaces them using a deterministic algorithm that generates canonical logic forms. Component encryption seeks to alter the semantics of individual circuit components using an encoding function, but preserves the overall circuit semantics by decoding signal values later in the circuit. Experiments were conducted to examine the performance of component fusion and component encryption against representative trials of subcircuit selection-and-replacement and Boundary Blurring, two previously defined methods for circuit obfuscation. Overall, results support the conclusion that both component fusion and component encryption generate more secure variants than previous methods and that these variants are more efficient in terms of required circuit delay and the power and area required for their implementation

Graph-based representations and coupled verification of VLSI schematics and layouts

Includes bibliographical references (p. 199-202).Work supported by the Air Force Office of Scientific Research. AFSOR 86-0164 Work supported by IBM and Analog Devices.Cyrus S. Bamji

Formally Verified Quantum Programming

The field of quantum mechanics predates computer science by at least ten years, the time between the publication of the Schrodinger equation and the Church-Turing thesis. It took another fifty years for Feynman to recognize that harnessing quantum mechanics is necessary to efficiently simulate physics and for David Deutsch to propose the quantum Turing machine. After thirty more years, we are finally getting close to the first general-purpose quantum computers based upon prototypes by IBM, Intel, Google and others. While physicists and engineers have worked on building scalable quantum computers, theoretical computer scientists have made their own advances. Complexity theorists introduced quantum complexity classes like BQP and QMA; Shor and Grover developed their famous algorithms for factoring and unstructured search. Programming languages researchers pursued two main research directions: Small-scale languages like QPL and the quantum lambda-calculi for reasoning about quantum computation and large-scale languages like Quipper and Q# for industrial-scale quantum software development. This thesis aims to unify these two threads while adding a third one: formal verification. We argue that quantum programs demand machine-checkable proofs of correctness. We justify this on the basis of the complexity of programs manipulating quantum states, the expense of running quantum programs, and the inapplicability of traditional debugging techniques to programs whose states cannot be examined. We further argue that the existing mathematical models of quantum computation make this an easier task than one could reasonably expect. In light of these observations we introduce QWIRE, a tool for writing verifiable, large scale quantum programs. QWIRE is not merely a language for writing and verifying quantum circuits: it is a verified circuit description language. This means that the semantics of QWIRE circuits are verified in the Coq proof assistant. We also implement verified abstractions, like ancilla management and reversible circuit compilation. Finally, we turn QWIRE and Coq\u27s abilities outwards, towards verifying popular quantum algorithms like quantum teleportation. We argue that this tool provides a solid foundation for research into quantum programming languages and formal verification going forward

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

An Analysis of the Conventional Wire Maintenance Methods and Transition Wire Integrity Programs Utilized in the Aviation Industry.

Aging aircraft wiring poses a significant threat to both commercial and military aircraft. Recent air disasters involving aging aircraft wiring have made it clear that aging wiring can be catastrophic. Aging of an electrical wiring system can result in loss of critical functions of equipment or loss of information regarding equipment operation. Either result can lead to an electrical failure causing smoke and fire, consequently being a danger to public health and aircraft safety. Conventional maintenance practices do not effectively manage aging wiring problems. More proactive methods are needed so that aircraft wiring failures can be anticipated and wiring systems can be repaired or replaced before failures occur. This thesis will identify the effects of aging wiring systems, the potential degradation to aircraft safety and regulations regarding aircraft wire safety. This thesis will evaluate the conventional wire maintenance practices and transition wire integrity programs in the aviation industry