Defense in Depth of Resource-Constrained Devices

The emergent next generation of computing, the so-called Internet of Things (IoT), presents significant challenges to security, privacy, and trust. The devices commonly used in IoT scenarios are often resource-constrained with reduced computational strength, limited power consumption, and stringent availability requirements. Additionally, at least in the consumer arena, time-to-market is often prioritized at the expense of quality assurance and security. An initial lack of standards has compounded the problems arising from this rapid development. However, the explosive growth in the number and types of IoT devices has now created a multitude of competing standards and technology silos resulting in a highly fragmented threat model. Tens of billions of these devices have been deployed in consumers\u27 homes and industrial settings. From smart toasters and personal health monitors to industrial controls in energy delivery networks, these devices wield significant influence on our daily lives. They are privy to highly sensitive, often personal data and responsible for real-world, security-critical, physical processes. As such, these internet-connected things are highly valuable and vulnerable targets for exploitation. Current security measures, such as reactionary policies and ad hoc patching, are not adequate at this scale. This thesis presents a multi-layered, defense in depth, approach to preventing and mitigating a myriad of vulnerabilities associated with the above challenges. To secure the pre-boot environment, we demonstrate a hardware-based secure boot process for devices lacking secure memory. We introduce a novel implementation of remote attestation backed by blockchain technologies to address hardware and software integrity concerns for the long-running, unsupervised, and rarely patched systems found in industrial IoT settings. Moving into the software layer, we present a unique method of intraprocess memory isolation as a barrier to several prevalent classes of software vulnerabilities. Finally, we exhibit work on network analysis and intrusion detection for the low-power, low-latency, and low-bandwidth wireless networks common to IoT applications. By targeting these areas of the hardware-software stack, we seek to establish a trustworthy system that extends from power-on through application runtime

Patent pledges, open IP, or patent pools? Developing taxonomies in the thicket of terminologies.

Recently, a range of organisations, including car and consumer electronics manufacturers, have applied so-called patent pledges. A patent pledge is a publicly announced intervention by patent-owning entities ('pledgers') to out-license active patents to the restricted or unrestricted public free from or bound to certain conditions for a reasonable or no monetary compensation. Despite growing research to better understand this phenomenon, the underlying terminology remains contradictory. We apply an inductive research approach using qualitative coding to analyse 60 patent pledges made by 80 organisations. Based on this analysis, we propose a three-dimensional taxonomy that distinguishes eight types of patent pledges. Extending this taxonomy using case examples, we then propose a generalised patent licensing taxonomy. This second taxonomy can be used to distinguish patent licensing strategies, including other frequently used approaches, such as patent pools and cross-licenses. Finally, we use the patent pledge taxonomy to illustrate how patent owners change their licensing strategies over time and how it can support strategic decision processes within an organisation. We contribute to the field of patent management by building an ontology of patent pledges through proposing a definition and eight types. The patent licensing taxonomy enables organisations to devise and choose licensing strategies, and to illustrate licensing approaches of competitors, for instance.This research project is funded by the Engineering and Physical Sciences Research Council (EPSRC) and the Research and Development Management Association (RADMA)

PRISM: an intelligent adaptation of prefetch and SMT levels

Current microprocessors include hardware to optimize some specifics workloads. In general, these hardware knobs are set on a default configuration on the booting process of the machine. This default behavior cannot be beneficial for all types of workloads and they are not controlled by anyone but the end user, who needs to know what configuration is the best one for the workload running. Some of these knobs are: (1) the Simultaneous MultiThreading level, which specifies the number of threads that can run simultaneously on a physical CPU, and (2) the data prefetch engine, that manages the prefetches on memory. Parallel programming models are here to stay, and one programming model that succeed in allowing programmers to easily parallelize applications is Open Multi Processing (OMP). Also, the architecture of microprocessors is getting more complex that end users cannot afford to optimize their workloads for all the architectural details. These architectural knobs can help to increase performance but it is needed an automatic and adaptive system managing them. In this work we propose an independent library for OpenMP runtimes to increase performance up to 220% (14.7% on average) while reducing dynamic power consumption up to 13% (2% on average) on a real POWER8 processor

Solutions for the optimization of the software interface on an FPGA-based NIC

The theme of the research is the study of solutions for the optimization of the software interface on FPGA-based Network Interface Cards. The research activity was carried out in the APE group at INFN (Istituto Nazionale di Fisica Nucleare), which has been historically active in designing of high performance scalable networks for hybrid nodes (CPU/GPU) clusters. The result of the research is validated on two projects the APE group is currently working on, both allowing fast prototyping for solutions and hardware-software co-design: APEnet (a PCIe FPGA-based 3D torus network controller) and NaNet (FPGA-based family of NICs mainly dedicated to real-time, low-latency computing systems such as fast control systems or High Energy Physics Data Acquisition Systems). NaNet is also used to validate a GPU-controlled device driver to improve network perfomances, i.e. even lower latency of the communication, while used in combination with existing user-space software. This research is also gaining results in the "Horizon2020 FET-HPC ExaNeSt project", which aims to prototype and develop solutions for some of the crucial problems on the way towards production of Exascale-level Supercomputers, where the APE group is actively contribuiting to the development of the network / interconnection infrastructure

The readying of applications for heterogeneous computing

High performance computing is approaching a potentially significant change in architectural design. With pressures on the cost and sheer amount of power, additional architectural features are emerging which require a re-think to the programming models deployed over the last two decades. Today's emerging high performance computing (HPC) systems are maximising performance per unit of power consumed resulting in the constituent parts of the system to be made up of a range of different specialised building blocks, each with their own purpose. This heterogeneity is not just limited to the hardware components but also in the mechanisms that exploit the hardware components. These multiple levels of parallelism, instruction sets and memory hierarchies, result in truly heterogeneous computing in all aspects of the global system. These emerging architectural solutions will require the software to exploit tremendous amounts of on-node parallelism and indeed programming models to address this are emerging. In theory, the application developer can design new software using these models to exploit emerging low power architectures. However, in practice, real industrial scale applications last the lifetimes of many architectural generations and therefore require a migration path to these next generation supercomputing platforms. Identifying that migration path is non-trivial: With applications spanning many decades, consisting of many millions of lines of code and multiple scientific algorithms, any changes to the programming model will be extensive and invasive and may turn out to be the incorrect model for the application in question. This makes exploration of these emerging architectures and programming models using the applications themselves problematic. Additionally, the source code of many industrial applications is not available either due to commercial or security sensitivity constraints. This thesis highlights this problem by assessing current and emerging hard- ware with an industrial strength code, and demonstrating those issues described. In turn it looks at the methodology of using proxy applications in place of real industry applications, to assess their suitability on the next generation of low power HPC offerings. It shows there are significant benefits to be realised in using proxy applications, in that fundamental issues inhibiting exploration of a particular architecture are easier to identify and hence address. Evaluations of the maturity and performance portability are explored for a number of alternative programming methodologies, on a number of architectures and highlighting the broader adoption of these proxy applications, both within the authors own organisation, and across the industry as a whole

HyperFPGA: SoC-FPGA Cluster Architecture for Supercomputing and Scientific applications

Since their inception, supercomputers have addressed problems that far exceed those of a single computing device. Modern supercomputers are made up of tens of thousands of CPUs and GPUs in racks that are interconnected via elaborate and most of the time ad hoc networks. These large facilities provide scientists with unprecedented and ever-growing computing power capable of tackling more complex and larger problems. In recent years, the most powerful supercomputers have already reached megawatt power consumption levels, an important issue that challenges sustainability and shows the impossibility of maintaining this trend. With more pressure on energy efficiency, an alternative to traditional architectures is needed. Reconfigurable hardware, such as FPGAs, has repeatedly been shown to offer substantial advantages over the traditional supercomputing approach with respect to performance and power consumption. In fact, several works that advanced the field of heterogeneous supercomputing using FPGAs are described in this thesis \cite{survey-2002}. Each cluster and its architectural characteristics can be studied from three interconnected domains: network, hardware, and software tools, resulting in intertwined challenges that designers must take into account. The classification and study of the architectures illustrate the trade-offs of the solutions and help identify open problems and research lines, which in turn served as inspiration and background for the HyperFPGA. In this thesis, the HyperFPGA cluster is presented as a way to build scalable SoC-FPGA platforms to explore new architectures for improved performance and energy efficiency in high-performance computing, focusing on flexibility and openness. The HyperFPGA is a modular platform based on a SoM that includes power monitoring tools with high-speed general-purpose interconnects to offer a great level of flexibility and introspection. By exploiting the reconfigurability and programmability offered by the HyperFPGA infrastructure, which combines FPGAs and CPUs, with high-speed general-purpose connectors, novel computing paradigms can be implemented. A custom Linux OS and drivers, along with a custom script for hardware definition, provide a uniform interface from application to platform for a programmable framework that integrates existing tools. The development environment is demonstrated using the N-Queens problem, which is a classic benchmark for evaluating the performance of parallel computing systems. Overall, the results of the HyperFPGA using the N-Queens problem highlight the platform's ability to handle computationally intensive tasks and demonstrate its suitability for its use in supercomputing experiments.Since their inception, supercomputers have addressed problems that far exceed those of a single computing device. Modern supercomputers are made up of tens of thousands of CPUs and GPUs in racks that are interconnected via elaborate and most of the time ad hoc networks. These large facilities provide scientists with unprecedented and ever-growing computing power capable of tackling more complex and larger problems. In recent years, the most powerful supercomputers have already reached megawatt power consumption levels, an important issue that challenges sustainability and shows the impossibility of maintaining this trend. With more pressure on energy efficiency, an alternative to traditional architectures is needed. Reconfigurable hardware, such as FPGAs, has repeatedly been shown to offer substantial advantages over the traditional supercomputing approach with respect to performance and power consumption. In fact, several works that advanced the field of heterogeneous supercomputing using FPGAs are described in this thesis \cite{survey-2002}. Each cluster and its architectural characteristics can be studied from three interconnected domains: network, hardware, and software tools, resulting in intertwined challenges that designers must take into account. The classification and study of the architectures illustrate the trade-offs of the solutions and help identify open problems and research lines, which in turn served as inspiration and background for the HyperFPGA. In this thesis, the HyperFPGA cluster is presented as a way to build scalable SoC-FPGA platforms to explore new architectures for improved performance and energy efficiency in high-performance computing, focusing on flexibility and openness. The HyperFPGA is a modular platform based on a SoM that includes power monitoring tools with high-speed general-purpose interconnects to offer a great level of flexibility and introspection. By exploiting the reconfigurability and programmability offered by the HyperFPGA infrastructure, which combines FPGAs and CPUs, with high-speed general-purpose connectors, novel computing paradigms can be implemented. A custom Linux OS and drivers, along with a custom script for hardware definition, provide a uniform interface from application to platform for a programmable framework that integrates existing tools. The development environment is demonstrated using the N-Queens problem, which is a classic benchmark for evaluating the performance of parallel computing systems. Overall, the results of the HyperFPGA using the N-Queens problem highlight the platform's ability to handle computationally intensive tasks and demonstrate its suitability for its use in supercomputing experiments

Low-cost IoT device for Fault Diagnosis in Rotating Machines

Orientador: Fabiano FruettTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Este trabalho apresenta um dispositivo de baixo custo com capacidade de mensuramento de vibrações utilizando como dispositivo transdutor de vibração um acelerômetro triaxial MEMS (Microelectromechanical Systems) aplicado a máquinas que operam numa velocidade de até 4000 RPM. Este dispositivo é capaz de obter o espectro com qualidade até a sexta ordem, de fácil instalação, com conectividade sem fio, facilitando sua inserção à internet das coisas (IoT - Internet of Things) e totalmente opensource. Para selecionar o acelerômetro adequado à nossa aplicação, testes de bancada foram realizados utilizando um motor BLDC e uma bomba centrífuga. Diversas perturbações foram inseridas nos testes, como desbalanceamento, carga, cavitação, entre outros. A resolução do sensor escolhido foi capaz de fornecer dados suficientes para o processamento. Diversas técnicas de análise de dados foram utilizadas, tais como análise de gráfico tipo waterfall, regressão logística, linear SVM e redes neurais artificiais, e em todas delas foi possível diagnosticar as perturbações inseridas. O sistema apresentado utiliza dados pré-processados em um microcontrolador ESP 32 de baixo custo. O microcontrolador recebe os dados temporais de vibração e velocidade da máquina objeto de estudo, calcula a FFT do sinal de vibração nos eixos X e Y e envia os dados para um servidor de IoT em nuvem que os armazenada. O envio desse sinal é feito através de uma comunicação sem fio utilizando a tecnologia IEEE 802.11, conhecida popularmente como Wi-Fi. O sistema final consiste em uma placa de aquisição dos sinais de vibração e um software que faz o pré-processamento do sinal de vibração. O custo da produção do protótipo do nosso dispositivo é inferior a US$30,00 e atendeu aos objetivos propostos de custo, integração IoT, processamento da FFT do sinal de vibração e armazenamento de dados em nuvem. O software foi desenvolvido utilizando apenas linguagens de programação gratuitas. Todo o projeto está disponível em um repositório online (open hardware e open software), sendo este aspecto parte da contribuição geral dessa teseAbstract: In this work is presented a low-cost device with capability of vibration measurement using as vibration transductor device a MEMS (Microelectromechanical Systems) triaxial accelerometer applied in machinery which operates under speed of until 4000 RPM. This device is able to obtain a quality spectrum until sixth order, with easy installation, with wireless connection, facilitating its insertion into the internet of things (IoT) and totally opensource. Bench tests were made to select the accelerometer suitable for our application. It was used one BLDC motor and one centrifugal pump. Several disturbances were inserted in the tests, as unbalance, load, cavitation, among others. The resolution of the sensor chosen was able to provide data enough for processing. Different data analysis techniques were used, such as waterfall chart analysis, logistic regression, linear SVM and artificial neural networks, and in all of them were possible to diagnosis the disturbances inserted. The presented system uses preprocessed data in a low-cost ESP32 microcontroller. The microcontroller receives the time domain vibration data and the speed of the study machine object, and calculates the FFT from the vibration signal in the X and Y-axis and sends these data to an IoT cloud server that stores it. This signal is sent through wireless communication using the IEEE 802.11 technology, popularly known as Wi-Fi. The final system consists of an acquisition vibration signal board and software that do the pre-processing of the vibration signal. The prototype manufacture cost of our device is less than US$ 30.00 and met the proposed objectives of cost, IoT integration, vibration signal FFT processing, and cloud storage. The software was developed using only free programming languages. All the project is available in an online repository (open hardware and open software), being this aspect a parcel of the general contribution of this thesisDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutora em Engenharia Elétric