Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.Comment: submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009

On chip interconnects for multiprocessor turbo decoding architectures

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Mapping interleaving laws to parallel turbo decoder architectures

For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints