Design of microprocessor-based hardware for number theoretic transform implementation

Number Theoretic Transforms (NTTs) are defined in a finite ring of integers Z (_M), where M is the modulus. All the arithmetic operations are carried out modulo M. NTTs are similar in structure to DFTs, hence fast FFT type algorithms may be used to compute NTTs efficiently. A major advantage of the NTT is that it can be used to compute error free convolutions, unlike the FFT it is not subject to round off and truncation errors. In 1976 Winograd proposed a set of short length DFT algorithms using a fewer number of multiplications and approximately the same number of additions as the Cooley-Tukey FFT algorithm. This saving is accomplished at the expense of increased algorithm complexity. These short length DFT algorithms may be combined to perform longer transforms. The Winograd Fourier Transform Algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo M is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (A/D) and a digital to analogue (D/A) converter allows real time digital signal processing

Integrated automatic modular measuring system

This paper describes a versatile automatic measuring system composed of discrete modules. The modules can operate in both stand‐alone and remote modes and are interconnected using an IEEE‐488 bus, allowing utilization of standard measurement apparatus and peripherals. The system design allows user optimization of the measurement procedure, which can thus be tailored to meet specific experimental requirements. The flexibility of this system is demonstrated by its application in spectroscopic ellipsometry

A Microprocessor-Based Control, Scheme for a PWM Voltage-Fed Inverter with an Induction Heating Tank Load

In this paper, the flexibility of programmed control logic is exploited in the close loop control of a PWM thyristor voltage fed inverter supplying an induction heating tank load. The microprocessor used in the control is the MC6809 to which is interfaced the SY6522 versatile interface adapter (VIA). The microprocessor-based scheme performs the dual function of generating the thyristor gating signals as well as estimating and applying control actions to maintain the load power factor at unity and the power delivered to the load at a desired set-point value. The schemed also provides power circuit over-current and over-voltage protection against adverse changes in the inverter input supply and the load. The estimation  of the control variables of the control scheme proportional plus integral controllers constitute the main control program while the application of thyristor gating signals and closed loop control actions are carried out in response  to interrupts external to the microprocessor unit. Illustrative steady state and transient circuit of an experimental model of the induction heater are given

Software and hardware implementation of the RSA public key cipher

Cryptographic systems and their use in communications are presented. The advantages obtained by the use of a public key cipher and the importance of this in a commercial environment are stressed. Two two main public key ciphers are considered. The RSA public key cipher is introduced and various methods for implementing this cipher on a standard, nondedicated, 8 bit microprocessor are investigated. The performance of the different algorithms are evaluated and compared. Various ways of increasing the performance are considered. The limitations imposed by the performance on the practical use of the cipher are discussed. The importance of the key to the security of the cipher is assessed. Different forms of attack are mentioned and a procedure for generating keys, which minimise the probability of a sucessful attack is presented. This procedure is implemented on a minicomputer. Use of the method on personal computers or microprocessors is examined. Methods for performing multiplication in hardware, with particular emphasis on the use of these methods in modular multiplication, are detailed. An algorithm for performing part of the encryption function in hardware and the hardware necessary for it is described. Different methods for implementing the hardware are discussed and one is choosen. A description of the hardware unit is given. The design and development of an application specific integrated circuit (ASIC) to perform key elements of the encryption function is described. The various stages of the design process are detailed. The results expected from this device and its integration into the overall encryption scheme are presented

Intelligent editor/printer enhancements

Microprocessor support hardware, software, and cross assemblers relating to the Motorola 6800 and 6809 process systems were developed. Pinter controller and intelligent CRT development are discussed. The user's manual, design specifications for the MC6809 version of the intelligent printer controller card, and a 132-character by 64-line intelligent CRT display system using a Motorola 6809 MPU, and a one-line assembler and disassembler are provided

The integrity of serial data highway systems

The Admiralty Surface Weapons Establishment (ASWE) have developed a Local Area Network System. This thesis describes the development of a replacement for this LAN system, based around 16 bit microprocessor hosts, as opposed to the minicomputers currently used. This change gave a substantial reduction in size, and allowed the new system to be installed on a ship and tested under operational conditions. Analysis of the data collected during the tests gave performance information on the ASWE system. The performance of this LAN is compared to that of other leading types of LAN. The design of a portable network controller/ monitor unit is presented, which may be manufactured as a standard controller for the ASWE Serial Highway

Audio time compansion for studio and performance synchronization

Thesis (M.S.V.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1987.Bibliography: leaves 46-47.by Marc Bayard LoCascio.M.S.V.S

Designing Testability Into An Existing Microprocessor Board

Master of ScienceDepartment of Electrical and Computer EngineeringThis thesis presents the hardware implementation of a microprocessor system built according to the microprocessor-controlled Built-In Self-Test (BIST) techniques as presented by Gordon [Gordon 1991 a]. It covers issues relating to the isolation of the edge connector and secondary board areas, to the use and function of a fieldprogrammable gate array (Logic Cell Array)n", to the implementation of electronic wraparounds, and to the general design of the software to support the testability features. In addition, it covers the general use of the ANSI/IEEE Std. 1149.1 test bus for diagnosis, isolation, and board-level partitioning