A Mixed-Signal Demodulator for a Low-Complexity IR-UWB Receiver: Methodology, Simulation and Design

This works presents an integrated 0.18μm CMOS 2-PPM demodulator based on a switched capacitor network for an Energy Detection Impulse-Radio UWB receiver. The circuit has been designed using a top-down methodology that allows to discover the impact of low-level non-idealities on system-level performance. Through the use of a mixed signal simulation environment, performance figures have been obtained which helped evaluate the influence at system-level of the non-idealities of the most critical block. Results show that the circuit allows the replacement of the ADC typically employed in Energy Detection receivers and provides about infinite equivalent quantization resolution. The demodulator achieves 190 pJ/bit at 1.8V

HW/SW Co-Design Framework für Hochgeschwindigkeits-OFDM Signalverarbeitung

Im Rahmen dieser Arbeit wurde ein HW/SW Co-Design Framework zur Erstellung angepasster Multiprozessor System-on-Chips entwickelt, womit sich für moderne OFDM-Systeme neue Kompromisse zwischen Leistungsfähigkeit und Flexibilität erzielen lassen. Anhand unterschiedlicher Experimente zur Hochgeschwindigkeits-OFDM Übertragung wurde die Funktionalität der Systeme nachgewiesen sowie Datenraten im Gb/s-Bereich erzielt, was bisher lediglich unflexiblen, dedizierten Schaltkreisen vorbehalten war

Microelectronic Implementation of Dicode PPM System Employing RS Codes

Optical fibre systems have played a key role in making possible the extraordinary growth in world-wide communications that has occurred in the last 25 years, and are vital in enabling the proliferating use of the Internet. Its high bandwidth capabilities, low attenuation characteristics, low cost, and immunity from the many disturbances that can afflict electrical wires and wireless communication links make it ideal for gigabit transmission and a major building block in the telecommunication infrastructure. A number of different techniques are used for the transmission of digital information between the transmitter and receiver sides in optical fibre system. One type of coding scheme is Pulse Position Modulation (PPM) in which the location of one pulse during 2M time slots is used to convey digital information from M bits. Although all the studies refer to advantages of PPM, it comes at a cost of large bandwidth and a complicated implementation. Therefore, variant PPM schemes have been proposed to transmit the data such as: Multiple Pulse Position Modulation (MPPM), Differential Pulse Position Modulation (DPPM), Pulse Interval Modulation (PIM), Digital Pulse Interval Modulation (DPIM), Dual Header Pulse Interval Modulation (DH-PIM), Dicode Pulse Position Modulation (DiPPM). The DiPPM scheme has been considered as a solution for the bandwidth consumption issue that other existing PPM formats suffer from. This is because it has a line rate that is twice that of the original data rate. DiPPM can be efficiently implemented as it employs two slots to transmit one bit of pulse code modulation (PCM). A PCM conversion from logic zero to logic one provides a pulse in slot RESET (R) and from one to zero provides a pulse in slot SET (S). No pulse is transmitted if the PCM data is unvarying. Like other PPM schemes, DiPPM suffers from three types of pulse detection errors wrong slot, false alarm, and erasure. The aim of this work was to build an error correction system, Reed Solomon (RS) code, which would overcome or reduce the error sources in the DiPPM system. An original mathematical program was developed using the Mathcad software to find the optimum RS parameters which can improve the DiPPM system error performance, number of photons and transmission efficiency. The results showed that the DiPPM system employing RS code offered an improvement over uncoded DiPPM of 5.12 dB, when RS operating at the optimum code rate of approximately ¾ and a codeword length of 25 symbols. Moreover, the error performance of the uncoded DiPPM is compared with the DiPPM system employing maximum likelihood sequence detector (MLSD), and RS code in terms of number of photons per pulse, transmission efficiency, and bandwidth expansion. The DiPPM with RS code offers superior performance compared to the uncoded DiPPM and DiPPM using MLSD, requiring only 4.5x103 photons per pulse when operating at a bandwidth equal to or above 0.9 times the original data rate. Further investigation took place on the DiPPM system employing RS code. A Matlab program and very high speed circuit Hardware Description language (VHDL) were developed to simulate the designed communication system. Simulation results were considered and agreed with the previous DiPPM theory. For the first time, this thesis presents the practical implementation for the DiPPM system employing RS code using Field Programmable Gate Array (FPGA)

Efficient arithmetic for high speed DSP implementation on FPGAs

The author was sponsored by EnTegra Ltd, a company who develop hardware and software products and services for the real time implementation of DSP and RF systems. The field programmable gate array (FPGA) is being used increasingly in the field of DSP. This is due to the fact that the parallel computing power of such devices is ideal for today’s truly demanding DSP algorithms. Algorithms such as the QR-RLS update are computationally intensive and must be carried out at extremely high speeds (MHz). This means that the DSP processor is simply not an option. ASICs can be used but the expense of developing custom logic is prohibitive. The increased use of the FPGA in DSP means that there is a significant requirement for efficient arithmetic cores that utilises the resources on such devices. This thesis presents the research and development effort that was carried out to produce fixed point division and square root cores for use in a new Electronic Design Automation (EDA) tool for EnTegra, which is targeted at FPGA implementation of DSP systems. Further to this, a new technique for predicting the accuracy of CORDIC systems computing vector magnitudes and cosines/sines is presented. This work allows the most efficient CORDIC design for a specified level of accuracy to be found quickly and easily without the need to run lengthy simulations, as was the case before. The CORDIC algorithm is a technique using mainly shifts and additions to compute many arithmetic functions and is thus ideal for FPGA implementation

Systemanalyse und Optimierung der Ultrabreitband-Übertragung

Die Arbeit untersucht Funk-Übertragung bei extrem großer Bandbreite. Zur Übertragung werden Komponenten benötigt, die über der gesamten Bandbreite konstante Eigenschaften aufweisen. Dies ist in der Realität nicht realisierbar und führt zu Signalstörungen. Die Arbeit modelliert solche Nicht-Idealitäten, bindet sie in ein messdatenbasiertes Systemmodell ein, untersucht das Systemverhalten und optimiert die Performance durch Methoden der Kompensation und optimaler Signalisierung

Architectures adaptatives basse consommation pour les communications sans-fil

This thesis work takes part in the connected objects theme, also known as the Internet of Things (IoT). It emerges from the Internet democratization since the early 2000's and the shift to highly mobile devices, made possible by the miniaturization of embedded systems. In this context, the energy efficiency is mandatory since today's projections are around tens of billions of connected devices in 2020. However for ease of deployment and usage, a large part of the data transfers in these networks is wireless, which implementation represents a significant part of the power consumption. Indeed, the energy efficiency question is addressed in general as a fine tuning of hardware architectures, which is often associated with a favorable technology evolution. Nevertheless, this design paradigm quickly reached its limits since it necessary implies a highly constrained sizing to be compatible with the worst operating conditions, even if they are not effective most of the time. It's typically the case with wireless communications since the radio channel is a medium characterized by a strong variability due to propagations effects and interferences. Thus, our study focused on the design of a communication chain whose link budget can be dynamically tuned depending on the actual signal attenuation, in order to reduce the system power consumption. The thesis has contributed to the design of a self-adaptive receiver dedicated to IEEE 802.15.4 standard, by proposing both a reconfigurable digital baseband architecture and an automatic control method of the operating mode. More precisely, the work relied on two approaches, the compressive sampling and the partial sampling, to reduce the data's size to process, decreasing the internal activity of arithmetics operators. In return, the demodulation processing needs a higher SNR, degrading in the same time the receiver sensitivity and thus the link budget. This solution, implemented in an STMicroelectronics CMOS 65 nm LP process, offers a low hardware overhead compared to conventional architecture with only 23,4 kgates. Thanks to the circuit physical model that has been developed, the power consumption for a packet demodulation is estimated to 278 uW when the baseband is fully activated. It can however be gradually decreased down to 119 uW, corresponding to a sensitivity reduction of 10 dB. Thus, the proposed digital baseband and its control loop save 30 % of energy in average in a typical use case.Ces travaux de thèse s'inscrivent dans la thématique des objets connectés, désormais connue sous le nom de Internet of Things (IoT). Elle trouve son origine dans la démocratisation d'Internet depuis le début des années 2000 et la migration vers des appareils hautement mobiles, rendue possible grâce à la miniaturisation des systèmes embarqués. Dans ce contexte, l'efficacité énergétique est primordiale puisque les projections actuelles parlent de dizaines de milliards de composants connectés à l'horizon 2020. Or pour une question de facilité de déploiement et d'usage, une grande partie des échanges de données dans ces réseaux s'effectue via une liaison sans-fil dont l'implémentation représente une part importante de la consommation. Effectivement, la question de l'efficacité énergétique est en général considérée comme un problème de perfectionnement des architectures matérielles, souvent associé à une évolution favorable de la technologie. Toutefois, ce paradigme atteint rapidement ses limites puisqu'il implique nécessairement un dimensionnement fortement contraint pour être compatible avec les pires conditions d'utilisation, même si elles ne sont pas effectives la plupart du temps. C'est typiquement le cas avec les communications sans-fil puisque le canal radio est un milieu caractérisé par une forte variabilité en raison des phénomènes de propagation et de la présence d'interférences. Notre étude a donc porté sur la conception d'une chaîne de transmission dont le budget de liaison peut être dynamiquement modifié en fonction de l'atténuation réelle du signal, afin de réduire la consommation du système. La thèse a notamment contribué à la mise au point d'un récepteur auto-adaptatif spécifique à la norme IEEE 802.15.4, en proposant à la fois une architecture de modem numérique reconfigurable et à la fois une méthode de contrôle automatique du point de fonctionnement. Plus précisément, le travail s'est appuyé sur deux approches, l'échantillonnage compressif et l'échantillonnage partiel, pour réduire la taille des données à traiter, diminuant ainsi l'activité interne des opérateurs arithmétiques. En contrepartie, le processus de démodulation nécessite un SNR supérieur, dégradant la sensibilité du récepteur et donc le budget de liaison. Cette solution, portée sur une technologie STMicroelectronics CMOS 65 nm LP, offre une faible empreinte matérielle vis-à-vis d'une architecture classique avec seulement 23,4 kcellules. Grâce au modèle physique du circuit qui a été développé, la consommation pour la démodulation d'un paquet est estimée à 278 uW lorsque le modem est intégralement utilisé. Elle peut toutefois être abaissée progressivement jusqu'à 119 uW, correspondant à une baisse de la sensibilité de 10 dB. Ainsi, le modem implémenté et sa boucle de contrôle permettent d'économiser en moyenne 30 % d'énergie dans un cas d'utilisation typique

Particle Swarm Optimization

Particle swarm optimization (PSO) is a population based stochastic optimization technique influenced by the social behavior of bird flocking or fish schooling.PSO shares many similarities with evolutionary computation techniques such as Genetic Algorithms (GA). The system is initialized with a population of random solutions and searches for optima by updating generations. However, unlike GA, PSO has no evolution operators such as crossover and mutation. In PSO, the potential solutions, called particles, fly through the problem space by following the current optimum particles. This book represents the contributions of the top researchers in this field and will serve as a valuable tool for professionals in this interdisciplinary field