2,176 research outputs found

    Design of Multistage Decimation Filters Using Cyclotomic Polynomials: Optimization and Design Issues

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    This paper focuses on the design of multiplier-less decimation filters suitable for oversampled digital signals. The aim is twofold. On one hand, it proposes an optimization framework for the design of constituent decimation filters in a general multistage decimation architecture. The basic building blocks embedded in the proposed filters belong, for a simple reason, to the class of cyclotomic polynomials (CPs): the first 104 CPs have a z-transfer function whose coefficients are simply {-1,0,+1}. On the other hand, the paper provides a bunch of useful techniques, most of which stemming from some key properties of CPs, for designing the proposed filters in a variety of architectures. Both recursive and non-recursive architectures are discussed by focusing on a specific decimation filter obtained as a result of the optimization algorithm. Design guidelines are provided with the aim to simplify the design of the constituent decimation filters in the multistage chain.Comment: Submitted to CAS-I, July 07; 11 pages, 5 figures, 3 table

    Efficient TV white space filter bank transceiver

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    Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy regulators. Further, with very high-speed ADCs and DACs becoming reality, the purpose of this paper is to present a transceiver front-end capable of simultaneously up- and downconverting a significant portion of the UHF band. The proposed approach takes a two-stage filter-bank conversion for implementation on state-of-the-art FPGAs. We present three different parameterisations, which are compatible with the 40 TVWS channels between 470 and 790MHz in Europe, and compare them in terms of complexity and latency

    A Reconfigurable Tile-Based Architecture to Compute FFT and FIR Functions in the Context of Software-Defined Radio

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    Software-defined radio (SDR) is the term used for flexible radio systems that can deal with multiple standards. For an efficient implementation, such systems require appropriate reconfigurable architectures. This paper targets the efficient implementation of the most computationally intensive kernels of two significantly different standards, viz. Bluetooth and HiperLAN/2, on the same reconfigurable hardware. These kernels are FIR filtering and FFT. The designed architecture is based on a two-dimensional arrangement of 17 tiles. Each tile contains a multiplier, an adder, local memory and multiplexers allowing flexible communication with the neighboring tiles. The tile-base data path is complemented with a global controller and various memories. The design has been implemented in SystemC and simulated extensively to prove equivalence with a reference all-software design. It has also been synthesized and turns out to outperform significantly other reconfigurable designs with respect to speed and area

    Advanced Algorithms for Satellite Communication Signal Processing

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    Dizertační práce je zaměřena na softwarově definované přijímače určené k úzkopásmové družicové komunikaci. Komunikační kanály družicových spojů zahrnujících komunikaci s hlubokým vesmírem jsou zatíženy vysokými úrovněmi šumu, typicky modelovaného AWGN, a silným Dopplerovým posuvem signálu způsobeným mimořádnou rychlostí pohybu objektu. Dizertační práce představuje možné postupy řešení výpočetně efektivní digitální downkonverze úzkopásmových signálů a systému odhadu kmitočtu nosné úzkopásmových signálů zatížených Dopplerovým posuvem v řádu násobků šířky pásma signálu. Popis navrhovaných algoritmů zahrnuje analytický postup jejich vývoje a tam, kde je to možné, i analytické hodnocení jejich chování. Algoritmy jsou modelovány v prostředí MATLAB Simulink a tyto modely jsou využity pro ověření vlastností simulacemi. Modely byly také využity k experimentálním testům na reálném signálu přijatém z družice PSAT v laboratoři experimentálních družic na ústavu radioelektroniky.The dissertation is focused on software defined receivers intended for narrowband satellite communication. The satellite communication channel including deep space communication suffers from a high level of noise, typically modeled by AWGN, and from a strong Doppler shift of a signal caused by the unprecedented speed of an object in motion. The dissertation shows possible approaches to the issues of computationally efficient digital downconversion of narrowband signals and the carrier frequency estimation of narrowband signals distorted by the Doppler shift in the order of multiples of the signal bandwidth. The description of the proposed algorithms includes an analytical approach of its development and, if possible, the analytical performance assessment. The algorithms are modeled in MATLAB Simulink and the models are used for validating the performance by the simulation. The models were also used for experimental tests on the real signal received from the PSAT satellite at the laboratory of experimental satellites at the department of radio electronics.

    Application of multirate digital filter banks to wideband all-digital phase-locked loops design

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    A new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity for hardware-processing speed by introducing parallel processing in the receiver. It is demonstrated here that the DPLL performance is identical to that of a PDPLL for both steady-state and transient behavior. A test signal with a time-varying Doppler characteristic is used to compare the performance of both the DPLL and the PDPLL

    Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

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    A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation

    Guest editorial for the special issue on software-defined radio transceivers and circuits for 5G wireless communications

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    Yichuang Sun, Baoyong Chi, and Heng Zhang, Guest Editorial for the Special Issue on Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications, published in IEEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63 (1): 1-3, January 2016, doi: https://doi.org/10.1109/TCSII.2015.2506979.Peer reviewedFinal Accepted Versio

    Adaptive interference suppression for DS-CDMA systems based on interpolated FIR filters with adaptive interpolators in multipath channels

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    In this work we propose an adaptive linear receiver structure based on interpolated finite impulse response (FIR) filters with adaptive interpolators for direct sequence code division multiple access (DS-CDMA) systems in multipath channels. The interpolated minimum mean-squared error (MMSE) and the interpolated constrained minimum variance (CMV) solutions are described for a novel scheme where the interpolator is rendered time-varying in order to mitigate multiple access interference (MAI) and multiple-path propagation effects. Based upon the interpolated MMSE and CMV solutions we present computationally efficient stochastic gradient (SG) and exponentially weighted recursive least squares type (RLS) algorithms for both receiver and interpolator filters in the supervised and blind modes of operation. A convergence analysis of the algorithms and a discussion of the convergence properties of the method are carried out for both modes of operation. Simulation experiments for a downlink scenario show that the proposed structures achieve a superior BER convergence and steady-state performance to previously reported reduced-rank receivers at lower complexity
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