Software Defined Radio Implementation of Carrier and Timing Synchronization for Distributed Arrays

The communication range of wireless networks can be greatly improved by using distributed beamforming from a set of independent radio nodes. One of the key challenges in establishing a beamformed communication link from separate radios is achieving carrier frequency and sample timing synchronization. This paper describes an implementation that addresses both carrier frequency and sample timing synchronization simultaneously using RF signaling between designated master and slave nodes. By using a pilot signal transmitted by the master node, each slave estimates and tracks the frequency and timing offset and digitally compensates for them. A real-time implementation of the proposed system was developed in GNU Radio and tested with Ettus USRP N210 software defined radios. The measurements show that the distributed array can reach a residual frequency error of 5 Hz and a residual timing offset of 1/16 the sample duration for 70 percent of the time. This performance enables distributed beamforming for range extension applications.Comment: Submitted to 2019 IEEE Aerospace Conferenc

Towards generic satellite payloads: software radio

Satellite payloads are becoming much more complex with the evolution towards multimedia applications. Moreover satellite lifetime increases while standard and services evolve faster, necessitating a hardware platform that can evolves for not developing new systems on each change. The same problem occurs in terrestrial systems like mobile networks and a foreseen solution is the software defined radio technology. In this paper we describe a way of introducing this concept at satellite level to offer to operators the required flexibility in the system. The digital functions enabling this technology, the hardware components implementing the functions and the reconfiguration processes are detailed. We show that elements of the software radio for satellites exist and that this concept is feasible

On-board demux/demod

To make satellite channels cost competitive with optical cables, the use of small, inexpensive earth stations with reduced antenna size and high powered amplifier (HPA) power will be needed. This will necessitate the use of high e.i.r.p. and gain-to-noise temperature ratio (G/T) multibeam satellites. For a multibeam satellite, onboard switching is required in order to maintain the needed connectivity between beams. This switching function can be realized by either an receive frequency (RF) or a baseband unit. The baseband switching approach has the additional advantage of decoupling the up-link and down-link, thus enabling rate and format conversion as well as improving the link performance. A baseband switching satellite requires the demultiplexing and demodulation of the up-link carriers before they can be switched to their assigned down-link beams. Principles of operation, design and implementation issues of such an onboard demultiplexer/demodulator (bulk demodulator) that was recently built at COMSAT Labs. are discussed

Direction of Arrival Estimation for Radio Positioning: a Hardware Implementation Perspective

Nowadays multiple antenna wireless systems have gained considerable attention due to their capability to increase performance. Advances in theory have introduced several new schemes that rely on multiple antennas and aim to increase data rate, diversity gain, or to provide multiuser capabilities, beamforming and direction finding (DF) features. In this respect, it has been shown that a multiple antenna receiver can be potentially used to perform radio localization by using the direction of arrival (DoA) estimation technique. In this field, the literature is extensive and gathers the results of almost four decades of research activities. Among the most cited techniques that have been developed, we find the so called high-resolution algorithms, such as multiple signal classification (MUSIC), or estimation of signal parameters via rotational invariance (ESPRIT). Theoretical analysis as well as simulation results have demonstrated their excellent performance to the point that they are usually considered as reference for the comparison with other algorithms. However, such a performance is not necessarily obtained in a real system due to the presence of non idealities. These can be divided into two categories: the impairments due to the antenna array, and the impairments due to the multiple radio frequency (RF) and acquisition front-ends (FEs). The former are strongly influenced by the manufacturing accuracy and, depending on the required DoA resolution, have to be taken into account. Several works address these issues in the literature. The multiple FE non idealities, instead, are usually not considered in the DoA estimation literature, even if they can have a detrimental effect on the performance. This has motivated the research work in this thesis that addresses the problem of DoA estimation from a practical implementation perspective, emphasizing the impact of the hardware impairments on the final performance. This work is substantiated by measurements done on a state-of-the-art hardware platform that have pointed out the presence of non idealities such as DC offsets, phase noise (PN), carrier frequency offsets (CFOs), and phase offsets (POs) among receivers. Particularly, the hardware platform will be herein described and examined to understand what non idealities can affect the DoA estimation performance. This analysis will bring to identify which features a DF system should have to reach certain performance. Another important issue is the number of antenna elements. In fact, it is usually limited by practical considerations, such as size, costs, and also complexity. However, the most cited DoA estimation algorithms need a high number of antenna elements, and this does not yield them suitable to be implemented in a real system. Motivated by this consideration, the final part of this work will describe a novel DoA estimation algorithm that can be used when multipath propagation occurs. This algorithm does not need a high number of antenna elements to be implemented, and it shows good performance despite its low implementation/computational complexity

Multichannel demultiplexer/demodulator technologies for future satellite communication systems

NASA-Lewis' Space Electronics Div. supports ongoing research in advanced satellite communication architectures, onboard processing, and technology development. Recent studies indicate that meshed VSAT (very small aperture terminal) satellite communication networks using FDMA (frequency division multiple access) uplinks and TDMA (time division multiplexed) downlinks are required to meet future communication needs. One of the critical advancements in such a satellite communication network is the multichannel demultiplexer/demodulator (MCDD). The progress is described which was made in MCDD development using either acousto-optical, optical, or digital technologies

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation