LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein

PROGRAMMABLE GENERATOR PRODUCING VIRTUAL ARBITRARY TEST PATTERNS

The suggested hybrid plan efficiently combines test compression with LBIST, where both techniques could work synergistically to provide top quality tests. It is composed of a straight line finite condition machine driving a suitable phase shifter, and it arrives with numerous features permitting this product to create binary sequences with preselected toggling (PRESTO) activity. We introduce a means to instantly select several controls from the generator offering simple and easy, precise tuning. This paper describes a minimal-power (LP) generator able to creating pseudorandom test designs with preferred toggling levels that has been enhanced fault coverage gradient in comparison using the best-to-date built-in self-test (BIST)-based pseudorandom test pattern machines. Exactly the same strategy is subsequently used to deterministically advice the generator toward test sequences with enhanced fault-coverage-to pattern-count ratios. In addition, this paper proposes an LP test compression way in which enables shaping the exam power envelope inside a fully foreseeable, accurate, and versatile fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. Experimental results acquired for industrial designs illustrate the practicality from the suggested test schemes and therefore are reported herein

Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

A MODIFIED FAULT COVERAGE ARCHITECTURE FOR A LOW POWER BIST TEST PATTERN GENERATOR USING LP-LFSR

This paper proposes low power pseudo random Test Pattern generation .This test pattern is run on the circuit under test for desired fault coverage. The power consumed by the chip under test is a measure of the switching activity of the logic inside the chip which depends largely on the randomness of the applied input stimulus. Reduced correlation between the successive vectors of the applied stimulus into the circuit under test can result in much higher power consumption by the device than the budgeted power. A new low power pattern generation technique is implemented using a modified conventional Linear Feedback Shift Register which can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit under Test (CUT) and hence power consumption is also reduced without any penalty in the hardware resources

REALIZATION OF LOW TRANSITION BASED PRPG FOR POWER OPTIMIZED APPLICATIONS

This paper proposes low power pseudo random test pattern generator. This produces the necessary test patterns which are used for running the circuit under test for detecting faults. Power consumption of the circuit under test is measured by switching activity of the inside logic which depends on the randomness of applied stimulus. Power consumption is greatly increased due to the reduction of correlation between the successive vectors of applied stimulus. A modified conventional linear feedback shift register is implemented for reducing power of circuit under test by generating the patterns by reducing the utilization of hard ware. The main intension of producing intermediate patterns is to reduce the conventional activity of primary inputs (PI) that which reduces the switching activities inside the CUT and by this power consumption is reduced without using huge hardware

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japa

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips

Tester for chosen sub-standard of the IEEE 802.1Q

Tato práce se zabývá analyzováním IEEE 802.1Q standardu TSN skupiny a návrhem testovacího modulu. Testovací modul je napsán v jazyku VHDL a je možné jej implementovat do Intel Stratix® V GX FPGA (5SGXEA7N2F45C2) vývojové desky. Standard IEEE 802.1Q (TSN) definuje deterministickou komunikace přes Ethernet sít, v reálném čase, požíváním globálního času a správným rozvrhem vysíláním a příjmem zpráv. Hlavní funkce tohoto standardu jsou: časová synchronizace, plánování provozu a konfigurace sítě. Každá z těchto funkcí je definovaná pomocí více různých podskupin tohoto standardu. Podle definice IEEE 802.1Q standardu je možno tyto podskupiny vzájemně libovolně kombinovat. Některé podskupiny standardu nemohou fungovat nezávisle, musí využívat funkce jiných podskupin standardu. Realizace funkce podskupin standardu je možná softwarově, hardwarově, nebo jejich kombinací. Na základě výše uvedených fakt, implementace podskupin standardu, které jsou softwarově související, byly vyloučené. Taky byly vyloučené podskupiny standardů, které jsou závislé na jiných podskupinách. IEEE 802.1Qbu byl vybrán jako vhodná část pro realizaci hardwarového testu. Různé způsoby testování byly vysvětleny jako DFT, BIST, ATPG a další jiné techniky. Pro hardwarové testování byla vybrána „Protocol Aware (PA)“technika, protože tato technika zrychluje testování, dovoluje opakovanou použitelnost a taky zkracuje dobu uvedení na trh. Testovací modul se skládá ze dvou objektů (generátor a monitor), které mají implementovanou IEEE 802.1Qbu podskupinu standardu. Funkce generátoru je vygenerovat náhodné nebo nenáhodné impulzy a potom je poslat do testovaného zařízeni ve správném definovaném protokolu. Funkce monitoru je přijat ethernet rámce a ověřit jejich správnost. Objekty jsou navrhnuty stejným způsobem na „TOP“úrovni a skládají se ze čtyř modulů: Avalon MM rozhraní, dvou šablon a jednoho portu. Avalon MM rozhraní bylo vytvořeno pro komunikaci softwaru s hardwarem. Tento modul přijme pakety ze softwaru a potom je dekóduje podle definovaného protokolu a „pod-protokolu “. „Pod-protokol“se skládá z příkazu a hodnoty daného příkazu. Podle dekódovaného příkazu a hodnot daných příkazem je kontrolovaný celý objekt. Šablona se používá na generování nebo ověřování náhodných nebo nenáhodných dat. Dvě šablony byly implementovány pro expresní ověřování nebo preempční transakce, definované IEEE 802.1Qbu. Porty byly vytvořené pro komunikaci mezi testovaným zařízením a šablonou podle daného standardu. Port „generátor“má za úkol vybrat a vyslat rámce podle priority a času vysílaní. Port „monitor“přijme rámce do „content-addressable memory”, která ověřuje priority rámce a podle toho je posílá do správné šablony. Výsledky prokázaly, že tato testovací technika dosahuje vysoké rychlosti a rychlé implementace.This master paper is dealing with the analysis of IEEE 802.1Q group of TSN standards and with the design of HW tester. Standard IEEE 802.1Qbu has appeared to be an optimal solution for this paper. Detail explanation of this sub-standard are included in this paper. As HW test the implementation, a protocol aware technique was chosen in order to accelerate testing. Paper further describes architecture of this tester, with detail explanation of the modules. Essential issue of protocol aware controlling objects by SW, have been resolved and described. Result proof that this technique has reached higher speed of testing, reusability, and fast implementation.

A Flexible Scan-in Power Control Method for Logic BIST

VLSIの微細化が進むと伴い，システムの大規模化・複雑化が進んでいる．また，システムテストやLSI出荷後のテスト(フィールドテスト)では，テストコストが増大する一方，厳しい制約下でテストを行う必要がある．例えば，少ないテストデータ量でかつチップ外部からの制御は少なくテストする必要があり，また，高品質なテストなために実際にユーザが使う回路のクロック速度でテストを行うことも求められる．これらの要求を満たすため，テスト容易化設計(Design For Testability：DFT)は不可欠であり，論理回路のフリップフロップ(Flip-Flop：FF)の値を直接観測・制御するスキャン設計は最も知られた手法である．更に，フィールドテストの厳しい制約を満すためLSIチップ上にテスタ機能を搭載してテストを行う，組込み自己テスト(Build-In Self-Test：BIST)が有効である．論理回路に対するBISTでは，よくスキャン設計を用いられる．簡単なLSI外部の制御でテストができ，また容易に実速度テストが行うことができるので，テストコスト削減やフィールドテスト等で有効である．しかし，スキャン設計を用いたBISTの問題点として，一般にテスト生成器が疑似ランダムに生成した高いトグル率(値が反転する確率50%)のテストパターンを使用するため，テストパターンをテスト対象回路に入力(スキャンイン動作)する際，多くのFFの値でトグルが発生し，通常の機能動作する時より消費電力が大きくなってしまう．消費電力が過度に増えると，回路内の発熱や電圧増減によるノイズ・遅延増減によって誤ったテスト結果をもたらすことになる．一方で，単純にテスト電力を下げることで低くなりすぎた場合，通常の機能動作では起きる故障が起こらなくなってしまい，不良の見逃しになる．したがって，回路毎に適切なテスト電力のレベルに合わせて，フレキシブルに電力を制御すべきである．また，テスト電力を制御する際，できるだけ制御回路の変更や面積オーバーヘッドが小さく，故障検出率に影響が少ない制御手法が良い．本論文では，フレキシブルなテスト電力を制御するために，テストパターンのトグル率を制御するスキャンイン電力制御手法を提案する．新たなスキャンイン電力低減回路(Phase Low Power Filter：PLPF)を用いたスキャンイン電力制御回路や制御手法を提案する．2章では，LSIテストの基礎となるスキャン設計やBISTの構造，テストの消費電力問題と対策について簡単に述べる．3章では，先行研究で提案したトグル率を低減する回路である従来のPLPFの説明を行い，動作や論理回路を最適化した新たなPLPFを提案した．提案したPLPFは，従来と同等なテストパターンのトグル率低減効果を実現し，論理回路の単純化と面積オーバーヘッドを削減できることを理論で説明した．4章では，フレキシブルなスキャンイン電力制御を行うための制御回路と制御手法について提案した．トグル率の低減レベルが異なるPLPFを複数用いて，スキャンシフト動作中に切り替えることでフレキシブルなスキャンイン電力を実現する．また，目標とするスキャンイン電力を達成するPLPFの切り替えるタイミングは多く存在するため，本論文では故障検出率と回路オーバーヘッドを考慮した3種類の制御手法(Basic，Swap，Moving)を提案した．5章では，10種類のベンチマーク回路に対して論理/故障シミュレーション結果と1つのベンチマーク回路で論理合成したときの面積結果を示した．論理シミュレーションでは，提案したPLPFのトグル率を測定し，従来のPLPFとほぼ同等なトグル率の低減効果を実現できることを確認した．そして，提案したスキャンイン電力制御手法は，目標スキャンイン電力(トグル率)より平均誤差±0.2%の精度で制御できることを示した．故障シミュレーションでは，単一縮退故障と遷移故障モデルを想定し，故障検出率を測定した．Moving制御手法で縮退故障検出率は平均8.41%，遷移故障検出率平均4.94%向上したことを示した．面積オーバーヘッド評価として，EDAツールを用いて制御回路を論理合成した時のセル数を算出した．その結果，従来のPLPFと提案したPLPFでは，約61%の面積を削減することができた．この章の結果より，提案したスキャンイン電力制御手法は，小面積オーバーヘッドで高い電力制御性と故障検出率の低下抑制効果を実現できることを示した．6章では，論理BISTにスキャンイン電力制御回路を搭載したCMOSのプロセスや対象回路規模が異なる2種類の試作チップを設計し，その測定結果を示した．試作チップの外部からBasic制御手法を用いてスキャンイン電力制御を行い，目標スキャンイン電力値と測定値である電流値・回路遅延に強い正負の相関を得ることができ，回路規模やプロセスの違いが有っても同様の結果が得られた．回路遅延は回路の発熱やテスト電力に大きく影響するため，回路遅延の制御ができていることは，電力制御ができていることを示し，この提案手法が誤ったテスト結果の回避に有効であることを示している．5章のシミュレーション結果と6章の試作チップ結果より，提案したスキャンイン電力制御手法の有効性の実証が示された．この提案手法を用いることで，フレキシブルなテスト電力制御かつ小面積オーバーヘッドで高信頼なテストの実現(特にフィールドテスト)，また，故障検出率低下抑制によるテスト時間短縮によってテストコスト削減の期待ができる．九州工業大学博士学位論文 学位記番号：情工博甲第333号 学位授与年月日：平成30年3月23日第1章 序論|第2章 高信頼なLSIテスト|第3章 スキャンイン電力低減|第4章 スキャンイン電力制御|第5章 シミュレーション評価|第6章 試作チップ評価 |第7章 結論九州工業大学平成29年

REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains