Timing and Carrier Synchronization in Wireless Communication Systems: A Survey and Classification of Research in the Last 5 Years

Timing and carrier synchronization is a fundamental requirement for any wireless communication system to work properly. Timing synchronization is the process by which a receiver node determines the correct instants of time at which to sample the incoming signal. Carrier synchronization is the process by which a receiver adapts the frequency and phase of its local carrier oscillator with those of the received signal. In this paper, we survey the literature over the last 5 years (2010–2014) and present a comprehensive literature review and classification of the recent research progress in achieving timing and carrier synchronization in single-input single-output (SISO), multiple-input multiple-output (MIMO), cooperative relaying, and multiuser/multicell interference networks. Considering both single-carrier and multi-carrier communication systems, we survey and categorize the timing and carrier synchronization techniques proposed for the different communication systems focusing on the system model assumptions for synchronization, the synchronization challenges, and the state-of-the-art synchronization solutions and their limitations. Finally, we envision some future research directions

Low Complexity Wireless Communication Digital Baseband Design

abstract: This thesis addresses two problems in digital baseband design of wireless communication systems, namely, those in Internet of Things (IoT) terminals that support long range communications and those in full-duplex systems that are designed for high spectral efficiency. IoT terminals for long range communications are typically based on Orthogonal Frequency-Division Multiple Access (OFDMA) and spread spectrum technologies. In order to design an efficient baseband architecture for such terminals, the workload profiles of both systems are analyzed. Since frame detection unit has by far the highest computational load, a simple architecture that uses only a scalar datapath is proposed. To optimize for low energy consumption, application-specific instructions that minimize register accesses and address generation units for streamlined memory access are introduced. Two parameters, namely, correlation window size and threshold value, affect the detection probability, the false alarm probability and hence energy consumption. Next, energy-optimal operation settings for correlation window size and threshold value are derived for different channel conditions. For both good and bad channel conditions, if target signal detection probability is greater than 0.9, the baseband processor has the lowest energy when the frame detection algorithm uses the longest correlation window and the highest threshold value. A full-duplex system has high spectral efficiency but suffers from self-interference. Part of the interference can be cancelled digitally using equalization techniques. The cancellation performance and computation complexity of the competing equalization algorithms, namely, Least Mean Square (LMS), Normalized LMS (NLMS), Recursive Least Square (RLS) and feedback equalizers based on LMS, NLMS and RLS are analyzed, and a trade-off between performance and complexity established. NLMS linear equalizer is found to be suitable for resource-constrained mobile devices and NLMS decision feedback equalizer is more appropriate for base stations that are not energy constrained.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Characterization, Avoidance and Repair of Packet Collisions in Inter-Vehicle Communication Networks

This work proposes a combined and accurate simulation of wireless channel, physical layer and networking aspects in order to bridge the gaps between the corresponding research communities. The resulting high fidelity simulations enable performance optimizations across multiple layers, and are used in the second part of this thesis to evaluate the impact of fast-fading channel characteristics on Carrier-Sense Multiple Access, and to quantify the benefit of successive interference cancellation

Characterization, Avoidance and Repair of Packet Collisions in Inter-Vehicle Communication Networks

This work proposes a combined and accurate simulation of wireless channel, physical layer and networking aspects in order to bridge the gaps between the corresponding research communities. The resulting high fidelity simulations enable performance optimizations across multiple layers, and are used in the second part of this thesis to evaluate the impact of fast-fading channel characteristics on Carrier-Sense Multiple Access, and to quantify the benefit of successive interference cancellation

Convergence of packet communications over the evolved mobile networks; signal processing and protocol performance

In this thesis, the convergence of packet communications over the evolved mobile networks is studied. The Long Term Evolution (LTE) process is dominating the Third Generation Partnership Project (3GPP) in order to bring technologies to the markets in the spirit of continuous innovation. The global markets of mobile information services are growing towards the Mobile Information Society. The thesis begins with the principles and theories of the multiple-access transmission schemes, transmitter receiver techniques and signal processing algorithms. Next, packet communications and Internet protocols are referred from the IETF standards with the characteristics of mobile communications in the focus. The mobile network architecture and protocols bind together the evolved packet system of Internet communications to the radio access network technologies. Specifics of the traffic models are shortly visited for their statistical meaning in the radio performance analysis. Radio resource management algorithms and protocols, also procedures, are covered addressing their relevance for the system performance. Throughout these Chapters, the commonalities and differentiators of the WCDMA, WCDMA/HSPA and LTE are covered. The main outcome of the thesis is the performance analysis of the LTE technology beginning from the early discoveries to the analysis of various system features and finally converging to an extensive system analysis campaign. The system performance is analysed with the characteristics of voice over the Internet and best effort traffic of the Internet. These traffic classes represent the majority of the mobile traffic in the converged packet networks, and yet they are simple enough for a fair and generic analysis of technologies. The thesis consists of publications and inventions created by the author that proposed several improvements to the 3G technologies towards the LTE. In the system analysis, the LTE showed by the factor of at least 2.5 to 3 times higher system measures compared to the WCDMA/HSPA reference. The WCDMA/HSPA networks are currently available with over 400 million subscribers and showing increasing growth, in the meanwhile the first LTE roll-outs are scheduled to begin in 2010. Sophisticated 3G LTE mobile devices are expected to appear fluently for all consumer segments in the following years

Cell search in frequency division : duplex WCDMA networks.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2006.Wireless radio access technologies have been progressively evolving to meet the high data rate demands of consumers. The deployment and success of voice-based second generation networks were enabled through the use of the Global System for Mobile Communications (GSM) and the Interim Standard Code Division Multiple Access (lS-95 CDMA) networks. The rise of the high data rate third generation communication systems is realised by two potential wireless radio access networks, the Wideband Code Division Multiple Access (WCDMA) and the CDMA2000. These networks are based on the use of various types of codes to initiate, sustain and terminate the communication links. Moreover, different codes are used to separate the transmitting base stations. This dissertation focuses on base station identification aspects of the Frequency Division Duplex (FDD) WCDMA networks. Notwithstanding the ease of deployment of these networks, their asynchronous nature presents serious challenges to the designer of the receiver. One of the challenges is the identification of the base station identity by the receiver, a process called Cell Search. The receiver algorithms must therefore be robust to the hostile radio channel conditions, Doppler frequency shifts and the detrimental effects of carrier frequency offsets. The dissertation begins by discussing the structure and the generation of WCDMA base station data along with an examination of the effects of the carrier frequency offset. The various cell searching algorithms proposed in the literature are then discussed and a new algorithm that exploits the correlation length structure is proposed and the simulation results are presented. Another design challenge presented by WCDMA networks is the estimation of carrier frequency offset at the receiver. Carrier frequency offsets arise due to crystal oscillator inaccuracies at the receiver and their effect is realised when the voltage controlled oscillator at the receiver is not oscillating at the same carrier frequency as that of the transmitter. This leads to a decrease in the receiver acquisition performance. The carrier frequency offset has to be estimated and corrected before the decoding process can commence. There are different approaches in the literature to estimate and correct these offsets. The final part of the dissertation investigates the FFT based carrier frequency estimation techniques and presents a new method that reduces the estimation error

Design of Intellectual Property-Based Hardware Blocks Integrable with Embedded RISC Processors

The main focus of this thesis is to research methods, architecture, and implementation of hardware acceleration for a Reduced Instruction Set Computer (RISC) platform. The target platform is a single-core general-purpose embedded processor (the COFFEE core) which was developed by our group at Tampere University of Technology. The COFFEE core alone cannot meet the requirements of the modern applications due to the lack of several components of which the Memory Management Unit (MMU) is one of the prominent ones. Since the MMU is one of the main requirements of today’s processors, COFFEE with no MMU was not able to run an operating system. In the design of the MMU, we employed two additional micro-Translation-Lookaside Buffers (TLBs) to speed up the translation process, as well as minimizing congestions of the data/instruction address translations with a unified TLB. The MMU is tightly-coupled with the COFFEE RISC core through the Peripheral Control Block (PCB) interface of the core. The hardware implementation, alongside some optimization techniques and post synthesis results are presented, as well.Another intention of this work is to prepare a reconfigurable platform to send and receive data packets of the next generation wireless communications. Hence, we will further discuss a recently emerged wireless modulation technique known as Non-Contiguous Orthogonal Frequency Division Multiplexing (NC-OFDM), a promising technique to alleviate spectrum scarcity problem. However, one of the primary concerns in such systems is the synchronization. To that end, we developed a reconfigurable hardware component to perform as a synchronizer. The developed module exploits Partial Reconfiguration (PR) feature in order to reconfigure itself. Eventually, we will come up with several architectural choices for systems with different limiting factors such as power consumption, operating frequency, and silicon area. The synchronizer can be loosely-coupled via one of the available co-processor slots of the target processor, the COFFEE RISC core.In addition, we are willing to improve the versatility of the COFFEE core even in industrial use cases. Hence, we developed a reconfigurable hardware component capable of operating in the Controller Area Network (CAN) protocol. In the first step of this implementation, we mainly concentrate on receiving, decoding, and extracting the data segment of a CAN-based packet. Moreover, this hardware block can reconfigure itself on-the-fly to operate on different data frames. More details regarding hardware implementation issues, as well as post synthesis results are also presented. The CAN module is loosely-coupled with the COFFEE RISC processor through one of the available co-processor block

Journal of Telecommunications and Information Technology, 2018, nr 4

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