Accurate and robust spectral testing with relaxed instrumentation requirements

Spectral testing has been widely used to characterize the dynamic performances of the electrical signals and devices, such as Analog-to-Digital Converters (ADCs) for many decades. One of the difficulties faced is to accurately and cost-effectively test the continually higher performance devices. Standard test methods can be difficult to implement accurately and cost effectively, due to stringent requirements. To relax these necessary conditions and to reduce test costs, while achieving accurate spectral test results, several new algorithms are developed to perform accurate spectral and linearity test without requiring precise, expensive instruments. In this dissertation, three classes of methods for overcoming the above difficulties are presented. The first class of methods targeted the accurate, single-tone spectral testing. The first method targets the non-coherent sampling issue on spectral testing, especially when the non-coherently sampled signal has large distortions. The second method resolves simultaneous amplitude and frequency drift with non-coherent sampling. The third method achieves accurate linearity results for DAC-ADC co-testing, and generates high-purity sine wave using the nonlinear DAC in the system via pre-distortion. The fourth method targets ultra-pure sine wave generation with two nonlinear DACs, two simple filters, and a nonlinear ADC. These proposed methods are validated by both simulation and measurement results, and have demonstrated their high accuracy and robustness against various test conditions. The second class of methods deals with the accurate multi-tone spectral testing. The first method in this class resolves the non-coherent sampling issue in multi-tone spectral testing. The second method in this class introduces another proposed method to deal with multi-tone impure sources in spectral testing. The third method generates the multi-tone sine wave with minimum peak-to-average power ratio, which can be implemented in many applications, such as spectral testing and signal analysis. Similarly, simulation and measurement results validate the functionality and robustness of these proposed methods. Finally, the third class introduces two proposed methods to accurately test linearity characteristics of high-performance ADCs using low purity sinusoidal or ramp stimulus in the presence of flicker noise. Extensive simulation results have verified their effectiveness to reduce flicker noise influence and achieve accurate linearity results

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Built-in self-test and self-calibration for analog and mixed signal circuits

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. This dissertation introduces two ADC testing algorithms and two ADC built-in self-test circuit implementations to test the ADC integral nonlinearity (INL) and differential nonlinearity (DNL) on-chip. In the first testing algorithm, the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) is developed for ADC built-in self-test, which eliminates the need for precision stimulus and reduces the overall test time. In this algorithm, the ADC is tested twice with a nonlinear ramp, instead of using a linear ramp signal. Therefore, the stimulus can be easily generated on-chip in a low-cost way. For the two ramps, there is a constant voltage shift in between. As the input stimulus linearity is completely relaxed, there is no requirement on the waveform of the input stimulus as long as it covers the ADC input range. In the meantime, the high-resolution ADC linearity is modeled with segmented parameters, which reduces the number of samples required for achieving high-precision test, thus saving the test time. As a result, the USER-SMILE algorithm is able to use less than 1 sample/code nonlinear stimulus to test high resolution ADCs with less than 0.5 least significant bit (LSB) INL estimation error, achieving more than 10-time test time reduction. This algorithm is validated with both board-level implementation and on-chip silicon implementation. The second testing algorithm is proposed to test the INL/DNL for multi-bit-per-stages pipelined ADCs with reduced test time and better test coverage. Due to the redundancy characteristics of multi-bit-per-stages pipelined ADC, the conventional histogram test cannot estimate and calibrate the static linearity accurately. The proposed method models the pipelined ADC nonlinearity as segmented parameters with inter-stage gain errors using the raw codes instead of the final output codes. During the test phase, a pure sine wave is sent to the ADC as the input and the model parameters are estimated from the output data with the system identification method. The modeled errors are then removed from the digital output codes during the calibration phase. A high-speed 12-bit pipelined ADC is tested and calibrated with the proposed method. With only 4000 samples, the 12-bit ADC is accurately tested and calibrated to achieve less than 1 LSB INL. The ADC effective number of bits (ENOB) is improved from 9.7 bits to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by more than 20dB after calibration. In the first circuit implementation, a low-cost on-chip built-in self-test solution is developed using an R2R digital-to-analog converter (DAC) structure as the signal generator and the voltage shift generator for ADC linearity test. The proposed DAC is a subradix-2 R2R DAC with a constant voltage shift generation capability. The subradix-2 architecture avoids positive voltage gaps caused by mismatches, which relaxes the DAC matching requirements and reduces the design area. The R2R DAC based BIST circuit is fabricated in TSMC 40nm technology with a small area of 0.02mm^2. Measurement results show that the BIST circuit is capable of testing a 15-bit ADC INL accurately with less than 0.5 LSB INL estimation error. In the second circuit implementation, a complete SAR ADC built-in self-test solution using the USER-SMILE is developed and implemented in a 28nm automotive microcontroller. A low-cost 12-bit resistive DAC with less than 12-bit linearity is used as the signal generator to test and calibrate a SAR ADC with a target linearity of 12 bits. The voltage shift generation is created inside the ADC with capacitor switching. The entire algorithm processing unit for USER-SMILE algorithm is also implemented on chip. The final testing results are saved in the memory for further digital calibration. Both the total harmonic distortion (THD) and the SFDR are improved by 20dB after calibration, achieving -84.5dB and 86.5dB respectively. More than 700 parts are tested to verify the robustness of the BIST solution

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V

M-sequenze based ultra-wideband radar and its application to crack detection in salt mines

Die vorliegende Dissertation beschreibt einen innovativen ultra-breitband (UWB)elektromagnetischen Sensor basierend auf einem Pseudo-Rauschverfahren.Der Sensor wurde für zerstörungsfreies Testen in zivilen Anwendungen entwickelt.Zerstörungsfreies Testen entwickelt sich zu einem immer wichtiger werdenden Bereich in Forschung und Entwicklung. Neben unzähligen weiteren Anwendungen und Technologien, besteht ein primäres Aufgabenfeld in der Überwachung und Untersuchung von Bauwerken und Baumaterialien durch berührungslose Messung aus der Ferne.Diese Arbeit konzentriert sich auf das Beispiel der Auflockerungszone im Salzgestein.Der Hintergrund und die Notwendigkeit, den Zustand der oberflächennahen Salzschichten in Salzminen kennen zu müssen, werden beleuchtet und die Messaufgabe anhand einfacher theoretischer Überlegungen beschrieben. Daraus werden die Anforderungen für geeignete UWB Sensoren abgeleitet. Die wichtigsten Eigenschaften sind eine sehr hohe Messband breite sowie eine sehr saubere Systemimpulsantwort frei von systematischen Gerätefehlern. Beide Eigenschaften sind notwendig, um die schwachen Rückstreuungen der Auflockerungen trotz der unvermeidlichen starken Oberflächenreflexion detektieren zu können.Da systematische Fehler bei UWB Geräten technisch nicht von vorne herein komplett vermeidbar sind, muss der Sensor eine Gerätekalibrierung erlauben, um solche Fehler möglichst gut zu unterdrücken.Aufgrund der genannten Anforderungen und den Nebenbedingungen der Messumgebung unter Tage, wurde aus den verschiedenen UWB-Technologien ein Prinzip ausgewählt, welches pseudozufällige Maximalfolgen als Anregungssignal benutzt. Das M-Sequenzkonzept dient als Ausgangpunkt für zahlreiche Weiterentwicklungen. Ein neues Sendemodul erweitert dabei die Messbandbreite auf 12~GHz. Die äquivalente Abtastrate wird um den Faktor vier auf 36~GHz erhöht, ohne den geringen Abtastjitter des ursprünglichen Konzepts zu vergrössern.Weiterhin wird die Umsetzung eines Zweitormesskopfes zur Erfassung von S-Parametern sowie einer automatische Kalibriereinheit beschrieben. Etablierte Kalibrierverfahren aus dem Bereich der Netzwerkanalyse werden kurz rekapituliert und die Adaption des 8-Term Verfahrens mit unbekanntem Transmissionsnormal für das M-Sequenzsystem beschrieben. Dabei werden Kennwerte vorgeschlagen, die dem Bediener unter Tage einfach erlauben, die Kalibrierqualität einzuschätzen und Hinweise auf mögliche Gerätefehler oder andere Probleme zu bekommen. Die Kalibriergenauigkeit des neuen Sensors im Labor wird mit der eines Netzwerkanalysators verglichen. Beide Geräte erreichen eine störungsfreie Dynamik von mehr als 60~dB in den Systemimpulsantworten für Reflexion und Transmission.Der neu entwickelte UWB Sensor wurde in zahlreichen Messungen in Salzminen in Deutschland getestet. Zwei Messbeispiele werden vorgestellt - ein sehr alter, kreisrunder Tunnel sowie ein ovaler Tunnelstumpf, welcher kurz vor den Messungen erst aufgefahren wurde. Messaufbauten und Datenverarbeitung werden beschrieben. Schließlich werden Schlussfolgerungen und Vorschläge für zukünftige Arbeiten mit dem neuen M-Sequenzsensor sowie der Messung von Auflockerungen im Salzgestein diskutiert.This dissertation describes an innovative ultra-wideband (UWB) electromagnetic sensor device based on a pseudo-noise principle developed in the context of non-destructive testing in civil engineering.Non-destructive testing is becoming a more and more important fieldfor researchers and engineers alike. Besides the vast field of possibleapplications and testing technologies, a prime and therefore typical topic is the inspection and monitoringof constructions and materials by means of contactless remote sensing techniques.This work focuses on one example the assessment of the disaggregation zone in salt rock tunnels.The background and relevance of knowing the state of salt rock layers near a tunnel's surface are explainedand simple theoretical considerations for requirements of suitable UWB sensor devices are shown. The most important sensor parameters are a very large measurement bandwidth and a very clean impulse response. The latterparameter translates into the mandatory application of calibration techniques to remove systematic errors of the sensor system itself. This enables detection of weak scattering responses from near-surface disaggregation despite the presence of a strong surface reflection.According to the mentioned requirements and other side conditions in salt mine environments an UWB sensor principlebased on pseudo-noise stimuli namely M-Sequences is selected as a starting point for system development. A newtransmitter frontend for extending the stimulus bandwidth up to 12~GHz is presented. Furthermore, a technique for increasing the (equivalent) sampling rate while keeping the stable and low-jitter sampling regime of the M-Sequencesapproach is introduced and its implementation is shown. Moreover, an automatic calibration unit for full two-port coaxial calibration of the new UWB sensor has been developed. Common calibration techniques from the area of vector network analysers are shortly reviewed and a reasonablealgorithm the 8-term method with an unknown line standard - is selected for the M-Sequences device. The 8-term method is defined in the frequency domain and is adapted for use with time domain devices. Some performance figures and comparisonwith calibration results from network analysers are discussed to show the effectiveness of the calibration.A spurious-free dynamic range of the time domain impulse responses in excess of 60~dB has been achieved for reflection as well as transmission measurements.The new UWB sensor was used in various real world measurements in different salt mines throughout Germany. Two measurementexamples are described and results from the disaggregation zone of a very old and a freshly cut tunnel will be presented. Measurement setup and data processing are discussed and finally some conclusions for future work on this topic are drawn

Ultrasonic sensor platforms for non-destructive evaluation

Robotic vehicles are receiving increasing attention for use in Non-Destructive Evaluation (NDE), due to their attractiveness in terms of cost, safety and their accessibility to areas where manual inspection is not practical. A reconfigurable Lamb wave scanner, using autonomous robotic platforms is presented. The scanner is built from a fleet of wireless miniature robotic vehicles, each with a non-contact ultrasonic payload capable of generating the A0 Lamb wave mode in plate specimens. An embedded Kalman filter gives the robots a positional accuracy of 10mm. A computer simulator, to facilitate the design and assessment of the reconfigurable scanner, is also presented. Transducer behaviour has been simulated using a Linear Systems approximation (LS), with wave propagation in the structure modelled using the Local Interaction Simulation Approach (LISA). Integration of the LS and LISA approaches were validated for use in Lamb wave scanning by comparison with both analytical techniques and more computationally intensive commercial finite element/diference codes. Starting with fundamental dispersion data, the work goes on to describe the simulation of wave propagation and the subsequent interaction with artificial defects and plate boundaries. The computer simulator was used to evaluate several imaging techniques, including local inspection of the area under the robot and an extended method that emits an ultrasonic wave and listens for echos (B-Scan). These algorithms were implemented in the robotic platform and experimental results are presented. The Synthetic Aperture Focusing Technique (SAFT) was evaluated as a means of improving the fidelity of B-Scan data. It was found that a SAFT is only effective for transducers with reasonably wide beam divergence, necessitating small transducers with a width of approximately 5mm. Finally, an algorithm for robot localisation relative to plate sections was proposed and experimentally validated

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Implementation and Characterization of Vibrotactile Interfaces

While a standard approach is more or less established for rendering basic vibratory cues in consumer electronics, the implementation of advanced vibrotactile feedback still requires designers and engineers to solve a number of technical issues. Several off-the-shelf vibration actuators are currently available, having different characteristics and limitations that should be considered in the design process. We suggest an iterative approach to design in which vibrotactile interfaces are validated by testing their accuracy in rendering vibratory cues and in measuring input gestures. Several examples of prototype interfaces yielding audio-haptic feedback are described, ranging from open-ended devices to musical interfaces, addressing their design and the characterization of their vibratory output