Design Of A Current Conveyor Analogue Multiplier For Energy Meter Using 0.35 Μm Mimos Cmos Technology

Analogue VLSI circuits are essential in many real-time signal processing applications as naturally occurring signals are analogue. The four-quadrant analogue multiplier is a key building block in analogue signal processing circuits. It is used to construct circuits like the modulator and waveform generator. The ideal output (Vout) of a multiplier is related to the inputs by Vout = KmVXVY, where Km is the multiplier gain with units of V-1, and VX and VY are input voltages. In reality, imperfections exist in the multiplier gain, resulting in offsets and nonlinearities. Important parameters such as power dissipation, supply voltage, input dynamic range, bandwidth, total harmonic distortion (THD) and linearity are used to assess the performance of an analogue multiplier. Nowadays both digital and analogue systems are routinely integrated onto single chips. Digital circuits commonly use low-voltage supply and employ techniques to reduce power consumption. Mixed analogue-digital circuits must be designed to operate in a low-voltage, low-power environment. Conventional analogue multipliers designed with low supply voltage suffer from performance trade-offs, resulting in low bandwidth and low dynamic range because the design of analogue circuits is a trade-off of various performance parameters such as power dissipation, supply voltage, gain, linearity and noise. The objective of this research is to design a low-voltage, low-power CMOS analogue multiplier that will address the above problems. The multiplier is designed in a modified bridged-triode scheme (MBTS) and uses current conveyors. As all analogue circuits can be decomposed into several sub-circuits, the performance of these sub-circuits decides the characteristics of the resultant circuit structure. The proposed circuit makes use of the current conveyor’s many special features, such as high output impedance and large bandwidth, to construct a low-voltage fourquadrant multiplier. The analogue multiplier designed in this research operates with a supply voltage of ±1V. The total harmonic distortion obtained from this multiplier is less than two percent, the input operating swing is up to 1Vpp, and the bandwidth achieved is more than 100MHz. It is designed using a 0.35μm technology from the Malaysian Institute of Microelectronics (MIMOS). In addition, an RMS-to-DC converter is designed using the same low-voltage design technique used for designing the adaptively-biased low-voltage current mirror (ABLVCM). Then an energy meter is designed using this analogue multiplier and the RMS-to-DC converter

Design Sign of Delta Sigma Wattmeter

Instantaneous power in a load is measured by multiplying the voltage across it by the current flowing through it. The multiplication is achieved in a delta sigma wattmeter by using two samplers rather than a multiplier. Sampling and multiplication are closely related. For example, double side-band suppressed carrier modulation can be produced by either multiplying an analogue signal with a sinusoidal carrier, or by sampling the analogue signal with a binary pulse train and filtering these samples. Alternatively these samples can be produced without a sampler if a multiplier is used. This is achieved by multiplying pulse train, whose binary values are arranged to be zero or unity, with the analogue signal. The delta-sigma wattmeter is given this name because the voltage developed across the load in which the power is to be measured is encoded by a delta sigma modulator, d.s.m into a binary waveform. The d.s.m. decoder is just a low-pass filte

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

The Analogue Computer as a Voltage-Controlled Synthesiser

This paper re-appraises the role of analogue computers within electronic and computer music and provides some pointers to future areas of research. It begins by introducing the idea of analogue computing and placing in the context of sound and music applications. This is followed by a brief examination of the classic constituents of an analogue computer, contrasting these with the typical modular voltage-controlled synthesiser. Two examples are presented, leading to a discussion on some parallels between these two technologies. This is followed by an examination of the current state-of-the-art in analogue computation and its prospects for applications in computer and electronic music

Probabilistic computing with future deep sub-micrometer devices: a modelling approach

An approach is described that investigates the potential of probabilistic "neural" architectures for computation with deep sub-micrometer (DSM) MOSFETs. Initially, noisy MOSFET models are based upon those for a 0.35 /spl mu/m MOS technology with an exaggerated 1/f characteristic. We explore the manifestation of the 1/f characteristic at the output of a 2-quadrant multiplier when the key n-channel MOSFETs are replaced by "noisy" MOSFETs. The stochastic behavior of this noisy multiplier has been mapped on to a software (Matlab) model of a continuous restricted Boltzmann machine (CRBM) - an analogue-input stochastic computing structure. Simulation of this DSM CRBM implementation shows little degradation from that of a "perfect" CRBM. This paper thus introduces a methodology for a form of "technology-downstreaming" and highlights the potential of probabilistic architectures for DSM computation