On the Existence of Combinational Networks with Arbitrary Multiple Redundancies

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / DAAB-07-72-C-025

Minimal test set for stuck-at faults in VLSI

Minimal test sets have the property that each input vector simultaneously tests several faults in a network. Existing techniques to determine a minimal set of detection tests rely heavily on complicated algebraic techniques. In this paper, two new methods are presented which do not require Boolean algebra or Karnaugh maps. The first is a graphical approach using fault folding graphs. The second is a design by inspection technique. This work follows the unique approach of first finding all the faults that can be detected by a single test. This tremendously reduces the work required to determine a minimal test set. The design by inspection method could be automated for programmatic generation of minimal stuck-at fault tests

A Minimum Cut Based Re-synthesis Approach

A new re-synthesis approach that benefits from min-cut based partitioning is proposed. This divide and conquer approach is shown to improve the performance of existing synthesis tools on a variety of benchmarks

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Single fault detection in combinational logic circuits

The material in this paper is divided into the following four chapters for convenience. Chapter 1 explains, how the idea of fault testing changed from testing the machine instructions to testing the hardware in logic circuits. Chapters 2, 3 and 4 present the different approaches considered, namely: 1. Path sensitizing and D-Algorithm method. 2. Tabular method. 3. Boolean difference method

Detection of hard faults in combinational logic circuits

ABSTRACT: Previous Work in identifying hard to test faults (HFs) -- The effect of reconvergent fanout and redundancy -- Testability measures (TMs)Using of ATPGs to detect HFs -- Previous use of cost in Testability analysis -- Review of automatic test pattern generation (ATPG) -- Fault modelling -- Single versus multiple path sensitization -- The four ATPG phases of deterministic gate level test generation -- Random test pattern generation and hybrid methods -- Review of the fan algorithm -- Backtrack reduction methods and the importance of heuristics -- Mixed graph -- binary decision diagram (GBDD) circuit model -- A review of graph techniques -- A review of binary decisions diagrams (BDDs) techniques -- gBDD -- graph binary decision diagrams -- Detection of hard faults using HUB -- Introduction to budgetary constraints -- The HUB algorithm -- Important HUB attributes -- Circuits characteristics of used for results -- Comparison of gBDD -- ATPG related results -- Fault simulation related results -- Hard fault detection

Logic Synthesis for Established and Emerging Computing

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported