The Gate Array Implementation of an Area Calculation Pipeline

A gate array is a semi-custom designed integrated circuit. The integrated circuit is designed by a customer and then turned over to a vendor to be manufactured. A single gate array is capable of replacing a full board or more of SSI and MSI components. An area calculation path of a special purpose computer that was designed into a gate array. LSI Logic Corporation was used as the vendor. The gate array was designed and then simulated with the Tegas Description Language. The simulation revealed a worst case timing problem which was corrected by adding an additional stage in the pipeline. The additional stage increased the time a first result is available at the output of the pipeline, but did not effect the rate at which successive results are available. The simulation and actual gate array prototype were proven with a calculated set of test vectors. The benefit of using gate arrays comes from reduced costs and increased reliabilit

Research in the effective implementation of guidance computers with large scale arrays Interim report

Functional logic character implementation in breadboard design of NASA modular compute

A Structured Design Methodology for High Performance VLSI Arrays

abstract: The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.Dissertation/ThesisPh.D. Electrical Engineering 201

Intellectual property strategy : analysis of the flash memory industry

Thesis (S.M.M.O.T.)--Massachusetts Institute of Technology, Sloan School of Management, Management of Technology Program, 2006.Page 150 blank.Includes bibliographical references (o, 120-121).This thesis studies the intellectual property strategy of companies in the flash memory industry, with special emphasis on technology and the development of nitride-based flash, a new and emerging type of memory technology. First, general perspectives and frameworks for licensing of patents and know-how are explored. Then, the participants in the flash memory industry are mapped to a product value chain, which is in turn mapped to an intellectual property value chain. We use a patent database analysis software IPVision in order to examine the patent portfolios of some of the memory chip companies. Analysis of the patent positions allows us to draw conclusions about the direction of technology development.by Tomoko H. Ogura.S.M.M.O.T

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Computer aids for the design of large scale integrated circuits.

The work described in this thesis is concerned with the development of CADIC (Computer Aided Design of Integrated Circuits), a suite of computer programs which allows the user to design integrated circuit layouts at the geometric level. Initially, a review of existing computer aids to integrated circuit design is carried out. Advantages and disadvantages of each computer aid is discused, and the approach taken by CADIC justified in the light of the review. The hardware associated with a design aid can greatly influence its performance and useability. For this reason, a critical review of available graphic terminals is also undertaken. The requirements, logistics, and operation of CADIC is then discussed in detail. CADIC provides a consise range of features to aid in the design and testing of integrated circuit layouts. The most important features are however CADIC's high efficiency in processing layout data, and the implementation of complete on-line design rule checking. Utilization of these features allows CADIC to substantially reduce the lengthy design turnaround time normally associated with manual design aids. Finally, the performance of CADIC is presented. Analysis of the results show that CADIC is very efficient at data processing, especially when small sections of the layout are considered. CADIC can also perform complete on-line design rule checking well within the time it takes the designer to start adding the next shape

NASA Tech Briefs Index 1980

Tech Briefs are short announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This Index to NASA Tech Briefs contains abstracts and four indexes -- subject,. personal author, originating Center, and Tech Brief number -- for 1980 Tech Briefs