Dual-frequency dual-inductor multiple-outputs (DF-DIMO) buck converter topologies with fully-integrated output filters

In multi-core DSPs, there is a need for multiple independent power supplies to power the digital cores. Each power supply needs to have fast dynamic response and must support a wide range of output voltage with up to hundreds of mA load current. In this dissertation, the key performance metrics in power converter design are introduced, the advantages and dis-advantages of the conventional power converter topology are analyzed and a new Dual-Frequency Dual-Inductor Multiple-Output (DF-DIMO) buck converter topology is presented to improve the limitations of the conventional topologies. The proposed topology employs a dual-phase 20-MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-output 100-MHz comparator-controlled fully-integrated output stage to reduce the capacitance required per output to 10 nF. To enable each output to handle up to 250-mA load with less than 40-mV voltage ripple, a 3rd-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance dynamic and cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency, and high-gain local output feedback to enhance DC load Regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65-nm CMOS technology with 1.8-V input, and outputs in the range of 0.6–1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40-mV output voltage ripple, 0.5-V/70-ns Dynamic Voltage Scaling (DVS), and settling time of less than 85 ns for 125-mA all with no cross regulations

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

Design and Switching Performance Evaluation of a 10 kV SiC MOSFET Based Phase Leg for Medium Voltage Applications

10 kV SiC MOSFETs are promising to substantially boost the performance of future medium voltage (MV) converters, ranging from MV motor drives to fast charging stations for electric vehicles (EVs). Numerous factors influence the switching performance of 10 kV SiC MOSFETs with much faster switching speed than their Si counterparts. Thorough evaluation of their switching performance is necessary before applying them in MV converters. Particularly, the impact of parasitic capacitors in the MV converter and the freewheeling diode is investigated to understand the switching performance more comprehensively and guide the converter design based on 10 kV SiC MOSFETs.A 6.5 kV half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is designed and fully validated to operate continuously at rated voltage with dv/dt up to 80 V/ns. Based on the phase leg, the impact of parasitic capacitors brought by the load inductor and the heatsink on the switching transients and performance of 10 kV SiC MOSFETs is investigated. Larger parasitic capacitors result in more oscillations, longer switching transients, as well as higher switching energy loss especially at low load current. As for the freewheeling diode, the body diode of 10 kV SiC MOSFETs is suitable to serve as the freewheeling diode, with negligible reverse recovery charge at various temperatures. The switching performance with and without the anti-parallel SiC junction barrier Schottky (JBS) diode is compared quantitatively. It is not recommended to add an anti-parallel diode for the 10 kV SiC MOSFET in the converter because it increases the switching loss

Control And Topology Improvements In Half-bridge Dc-dc Converters

Efficiency and transient response are two key requirements for DC-DC converters. Topology and control are two key topics in this dissertation. A variety of techniques for DC-DC converter performance improvement are presented in this work. Focusing on the efficiency issue, a variety of clamping techniques including both active and passive methods are presented after the ringing issues in DC-DC converters are investigated. By presenting the clamping techniques, a big variety of energy management concepts are introduced. The active bridge-capacitor tank clamping and FET-diode-capacitor tank clamping are close ideas, which transfer the leakage inductor energy to clamping capacitor to prevent oscillation between leakage inductor and junction capacitor of MOSFETs. The two-FET-clamping tank employs two MOSFETs to freewheeling the leakage current when the main MOSFETs of the half-bridge are both off. Driving voltage variation on the secondary side Synchronous Rectifier (SR) MOSFETs in self-driven circuit due to input voltage variation in bus converter applications is also investigated. One solution with a variety of derivations is proposed using zerner-capacitor combination to clamping the voltage while maintaining reasonable power losses. Another efficiency improvement idea comes from phase-shift concept in DC-DC converters. By employing phase-shift scheme, the primary side and the secondary side two MOSFETs have complementary driving signals respectively, which allow the MOSFET to be turned on with Zero Voltage Switching (ZVS). Simulation verified the feasibility of the proposed phase-shifted DC-DC converter. From the control scheme point of view, a novel peak current mode control concept for half-bridge topologies is presented. Aiming at compensating the imbalanced voltage due to peak current mode control in symmetric half-bridge topologies, an additional voltage compensation loop is used to bring the half-bridge capacitor voltage back to balance. In the proposed solutions, one scheme is applied on symmetric half-bridge topology and the other one is applied on Duty-cycle-shifted (DCS) half-bridge topology. Both schemes employ simple circuitry and are suitable for integration. Loop stability issues are also investigated in this work. Modeling work shows the uncompensated half-bridge topology cannot be stabilized under all conditions and the additional compensation loop helps to prevent the voltage imbalance effectively

Switching Performance Evaluation, Design, and Test of a Robust 10 kV SiC MOSFET Based Phase Leg for Modular Medium Voltage Converters

10 kV SiC MOSFETs are one of the most promising power semiconductor devices for next-generation high-performance modular medium voltage (MV) converters. With extraordinary device characteristics, 10 kV SiC MOSFETs also bring a variety of challenges in the design and test of MV converters. To tackle these inherent challenges, this dissertation focuses on a robust half bridge (HB) phase leg based on 10 kV SiC MOSFETs for modular MV converters. A baseline design and test of the phase leg is established first as the foundation of the research in this dissertation. Thorough evaluation of 10 kV SiC MOSFETs’ switching performance in a phase leg is necessary before applying them in MV converters. The impact of parasitic capacitors and the freewheeling diode is investigated to understand the switching performance more extensively and guide the converter design. One non-negligible challenge is the flashover fault resulting from the premature insulation breakdown, a short circuit fault with extremely fast transients. A device model is established to analyze the behavior of 10 kV SiC MOSFETs when the fault occurs in a phase leg thoroughly. Subsequently, the gate driver and protection design considerations are summarized to achieve lower short circuit current and overvoltage and ensure the survival of the MOSFET that in ON state when the fault happens. Furthermore, it is challenging to design the overcurrent/short circuit protection with fast response and strong noise immunity under fast switching transients for 10 kV SiC MOSFETs. The noise immunity of the desaturation (desat) protection is studied quantitatively to provide design guidelines for noise immunity enhancement. Then, the protection scheme based on desat protection is developed and validated withimmunity, the strong noise immunity of the developed protection is also successfully validated. In addition, a simple test scheme is proposed and validated experimentally, in order to qualify the HB phase leg based on the 10 kV SiC MOSFET comprehensively for the modular MV converter applications. The test scheme includes the ac-dc continuous test with two phase legs in series to create the testing condition similar to what is generated in a modular MV converter, especially the high dv/dt. The test scheme can fully test the capability of the phase leg to withstand high dv/dt and its resulting noise

Analysis of a PWM Resonant Buck Chopper for Use as a Ship Service Converter Module

The Navy's interest in implementing a DC Zonal Electric Distribution System (DC ZEDS) in the next generation of surface combatant has motivated considerable research work into dc-dc converters. The switching frequency of a hard-switched dc-dc converter is limited by the maximum admissible switching losses allowed by the switch, heat sink, and cooling process. Also, hard- switched converters contribute significant Electromagnetic Interference (EMI) concerns for the system. This study provides a background analysis into resonant converters which utilize zero-voltage-switching and zero-current-switching techniques to mitigate the aforementioned concerns and facilitate high-bandwidth control loops. In particular, one candidate circuit is identified which can be readily realized using existing hardware and a straightforward control. The report documents the modes of operation of the circuit, sets forth the governing differential equation and mode-transition conditions, examines an ACSL simulation representation of the circuit, formulates design criteria for component selection, identifies key fabrication nuances, and documents a PSpice simulation of the circuit. Both simulation models are used to explain the operating modes of the circuit, provide insight into parameter selection, and ultimately to design the proper control of the circuit.Prepared for: Naval Surface Warfare Center (NSWC) Annapolis Det.N00167-98-WR-80279Approved for public release; distribution is unlimited

Single-Stage Power Electronic Converters with Combined Voltage Step-Up/Step-Down Capability

Power electronic converters are typically either step-down converters that take an input voltage and produce an output voltage of low amplitude or step-up converters that take an input voltage and produce an output voltage of higher amplitude. There are, however, applications where a converter that can step-up voltage or step-down voltage can be very useful, such as in applications where a converter needs to operate under a wide range of input and output voltage conditions such as a grid-connected solar inverter. Such converters, however, are not as common as converters that can only step down or step up voltage because most applications require converters that need to only step down voltage or only step up voltage and such converters have better performance within a limited voltage range than do converters that are designed for very wide voltage ranges. Nonetheless, there are applications where converters with step-down and step-up capability can be used advantageously. The main objectives of this thesis are to propose new power electronic converters that can step up voltage and step down voltage and to investigate their characteristics. This will be done for two specific converter types: AC/DC single-stage converters and DC-AC inverters. In this thesis, two new AC/DC single-stage converters and a new three-phase converter are proposed and their operation and steady-state characteristics are examined in detail. The feasibility of each new converter is confirmed with results obtained from an experimental prototype and the feasibility of a control method for the inverter is confirmed with simulation work using commercially available software such as MATLAB and PSIM

Periodic perturbation method for controlling chaos for a positive output DC-DC luo converter

Abstract: A simple, non-feedback method of controlling chaos is implemented for a DC-DC converter. The weak periodic perturbation (WPP) is the control technique applied to stabilize an unstable orbit in a current-mode controlled Positive Output Luo (POL) DC-DC converter operating in a chaotic regime. With WPP, the operation of the converter is limited to stable period-1 orbit that exists in the original chaotic attractor. The proposed control strategy is implemented using simulations and the results are verified with hardware setup. The experimental results of the converter with WPP control are presented which shows the effectiveness of the control strategy

Three-phase ac-dc buck-boost converter with a reduced number of switches

A single-switch, single-stage, three-phase ac-dc buck-boost converter suitable for medium-voltage applications is proposed. Basic relations that govern steady-state converter operation are established, confirmed using PSCAD/EMTDC simulations, and substantiated experimentally. Simulation and experimental results establish that the proposed converter has good dynamic performance in buck and boost modes, with near unity input power factor

Digitally Controlled Zero-Voltage-Switching Quasi-Resonant Buck Converter

ABSTRACT Digitally-Controlled Two-Phase Zero-Voltage-Switching Quasi-Resonant Buck Converter Brian Luc This thesis entails the design, construction, and performance analysis of a digitally-controlled two-phase Zero-Voltage Switching Quasi-Resonant (ZVS-QR) buck converter. The converter is aimed to address the issues associated with powering CPUs operating at lower voltage and high current. To evaluate its performance, the Two-Phase ZVS-QR buck converter is compared against a traditional Two-Phase buck converter. The design procedure required to implement both converters through utilizing the characterization curve and formulas derived from their circuit configurations will be presented. Computer simulation of the Two-Phase ZVS-QR buck converter is provided to exhibit its operation and potential for use in low voltage and high current applications. In addition, hardware prototypes for both ZVS-QR and traditional buck converters are constructed utilizing a Programmable Interface Controller (PIC). Results from hardware tests demonstrate the success of using digital controller for the 60W 12VDC to 1.5VDC ZVS-QR buck converter. Merits and drawbacks based on the operation and performance of both converters will also be assessed and described. Further work to improve the performance of ZVS-QR will also be presented. Keywords: Buck Converter; Zero-Voltage-Switching; Multi-Phase; Efficiency; Switching Los