Class-E Power Amplifiers in Modern RF Transmitters

Power amplifiers have been playing a vital role in most wireless communication systems. In order to improve efficiency of wireless systems, advanced transmitter architectures, such as Doherty amplifiers, outphasing amplifiers, supply voltage modulation techniques are widely used. The goal of this work is to develop novel techniques for building load modulation transmitters based on class-E power amplifiers. The first contribution is an analytical model for derivation load network parameters. The proposed model derives the parameters for both the peak and back-off power levels providing high efficiency. The proposed model demonstrates, that class-E PA with shunt capacitance and shunt filter is capable of providing high drain efficiency for back-off output power levels. The second contribution is a design of a wideband class-E power amplifier (PA) with shunt capacitance and shunt filter. The broadband operation has been achieved by application of the double reactance compensation technique. Simulated and experimental results are presented. The performance of the fabricated PA is compared with existing wideband PAs. The third contribution is application of the proposed technique to outphasing PA design. The designed outphasing PA was optimized, fabricated and tested. A possibility to extend the operational bandwidth of the PA is considered. Also the application of the proposed technique to Doherty PA design is demonstrated. The fourth contribution is linearization of outphasing PA. Firstly, an analytical model describing the nonlinearity of nonisolated combiners under amplitude imbalance is presented. Secondly, a novel phase-only predistortion technique for class-E outphasing PAs is proposed. Thirdly, linearization of the fabricated outphasing PA based on memory polynomial model is demonstrated using a 64QAM OFDM modulated signal with 20 MHz bandwidth. Overall, this work provides novel techniques for load modulation transmitter design based on class-E power amplifiers with shunt capacitance and shunt filter

Phase-Only Digital Predistortion Technique for Class-E Outphasing Power Amplifiers

Efficient and linear power amplifiers (PA) are an essential part of forthcoming 5G wireless systems. Outphasing class-E PAs offer high power efficiency and an option for higher efficiency cellular networks. However, they employ signal component separators, which split the signal into two paths. In order to efficiently recombine the signal, nonlinear power combiners are used. This paper proposes a novel phase-only predistortion technique for outphasing class-E PAs. The predistortion coefficients can be extracted based on AMAM characteristics of the output signal and an analytical model of an outphasing Class E PA. The suggested technique has been validated by simulation of an outphasing power amplifier in ADS Ptolemy software. It is shown that applying this technique to a 16QAM OFDM modulated signal with 20 MHz bandwidth improves error vector magnitude (EVM) from 10.39% to 2.43% compared to the signal without predistortion

Linear Operation of Switch-Mode Outphasing Power Amplifiers

Radio transceivers are playing an increasingly important role in modern society. The ”connected” lifestyle has been enabled by modern wireless communications. The demand that has been placed on current wireless and cellular infrastructure requires increased spectral efficiency however this has come at the cost of power efficiency. This work investigates methods of improving wireless transceiver efficiency by enabling more efficient power amplifier architectures, specifically examining the role of switch-mode power amplifiers in macro cell scenarios. Our research focuses on the mechanisms within outphasing power amplifiers which prevent linear amplification. From the analysis it was clear that high power non-linear effects are correctable with currently available techniques however non-linear effects around the zero crossing point are not. As a result signal processing techniques for suppressing and avoiding non-linear operation in low power regions are explored. A novel method of digital pre-distortion is presented, and conventional techniques for linearisation are adapted for the particular needs of the outphasing power amplifier. More unconventional signal processing techniques are presented to aid linearisation of the outphasing power amplifier, both zero crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear regions of the amplifiers. In combination with digital pre-distortion the techniques will improve linearisation efforts on outphasing systems with dynamic range and bandwidth constraints respectively. Our collaboration with NXP provided access to a digital outphasing power amplifier, enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural modelling and linearisation efforts. The collaboration resulted in a bench mark for linear wideband operation of a digital outphasing power amplifier. The complimentary linearisation techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in both simulated and practical outphasing test benches. Initial results are promising and indicate that the benefits they provide are not limited to the outphasing amplifier architecture alone. Overall this thesis presents innovative analysis of the distortion mechanisms of the outphasing power amplifier, highlighting the sensitivity of the system to environmental effects. Practical and novel linearisation techniques are presented, with a focus on enabling wide band operation for modern communications standards

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Power Efficiency Enhancement and Linearization Techniques for Power Amplifiers in Wireless Communications

Wireless communication systems require Power Amplifiers (PAs) for signal transmissions. The trade-off between power efficiency and nonlinear distortion in PAs degrades the communication performance. Thus, power efficiency and nonlinearity are two main concerns of operating PAs in communication systems. Nonlinear behavioral models are typically used to quantify and mitigate the distortion effects of PAs on communication systems. This dissertation presents an estimation approach for modeling and linearizing the PA Amplitude-to-Amplitude (AM/AM) nonlinearity using the design specifications of PAs, such as gain, the third-order intercept point, and 1dB compression point. Furthermore, an enhanced approach for modeling solid-state power amplifiers is developed by modifying the Saleh empirical model. The Envelope Tracking (ET) technique for PAs has been a popular power efficiency enhancement in modern cellular systems. However, the time-varying effects of the supply voltage impacts the PA linearity. Therefore, an accurate behavioral model for PA with ET has become an important research effort to characterize the effect of dynamic supply voltage on both the amplitude and phase nonlinearities. Furthermore, the empirical models of ET PAs are widely used to improve PAs linearity by using Digital Predistortion (DPD). This dissertation develops an extended modeling approach to characterize the AM/AM and Amplitude-to-Phase (AM/PM) conversions as well as account for the impact of the time-varying supply voltage on the ET PAs. Memory effects, due to energy storage elements (e.g. capacitors and inductors) in ET PA circuits in addition to the temperature variation of integrated circuit, are modeled using digital filters (finite impulse-response filters) in series with the static AM/AM and static AM/PM nonlinearities. A least-squares approach is mathematically derived for estimating the model coefficients of ET PAs. The model identification of many coefficients requires high computational cost in Float Point Operations (FLOPS), such as multipliers and adders. In addition, the computational cost in FLOPs of a complex number is equivalent to (2-6) times the cost of real numbers. The estimation complexity of the ET PAs model in this work requires around half the number of FLOPS compared to the state-of-the-art behavioral models. This is because the modeling approach in this work consists of real coefficients and a lower number of model parameters. A DPD model is derived in this dissertation to compensate for both the AM/AM and AM/PM nonlinear distortions in ET PAs. A dual-input single-output function architecture is calculated for the DPD model to compensate for the nonlinearities in the AM/AM and AM/PM conversions contributed by the time-varying supply voltage in the ET system. Both the proposed AM/AM and AM/PM DPD models exhibit lower numbers of coefficients, which result in reduction of the identification complexity compared to the state-of-the-art DPD models. The proposed behavioral models of the ET PA and DPD are both evaluated in the time and frequency domains, as well as compared to the state-of-the-art models in terms of model accuracy and estimation complexity

Evaluación de los nuevos mecanismos de adaptación basados en redes reconfigurables para la mejora de la eficiencia en sistemas de comunicaciones móviles

En los sistemas de comunicaciones móviles actuales y futuros se está apostando por un proceso de investigación asociado a la obtención de sustanciales mejoras en el uso eficiente de la potencia de los transmisores, en especial a aquellos utilizados en los sistemas portátiles, donde el uso eficiente en el consumo de la batería es fundamental. Los sistemas de primera y segunda generación empleaban modulaciones de envolvente constante (con poca eficiencia espectral), que permitían operar los amplificadores de potencia (PA) en zona de saturación manteniendo buenos valores de eficiencia sin degradar calidad de la señal. Sin embargo, los nuevos sistemas de comunicaciones 3G, 4G, emplean esquemas de modulación más eficientes para proporcionar las tasas de datos y calidad de servicio demandadas. Estas modulaciones, como por ejemplo OFDM, están basadas en señales de envolvente no constante, que no pueden ser amplificadas eficientemente utilizando las arquitecturas clásicas, y por lo tanto requieren grandes back-offs para mantener unos niveles de linealidad en la señal de salida aceptables. A todo esto hay que sumarle el incremento en los anchos de banda de las señales, así como la posibilidad de funcionar en distintas bandas frecuenciales y usando distintos tipos de señales, lo que añade complejidad adicional al diseño de los front-ends de RF. Otro de los factores que afectará a la eficiencia energética en transmisores inalámbricos es el efecto de variación de la impedancia de carga. El diseño de los PAs se realiza habitualmente considerando una carga fija de 50 ohmios. Sin embargo, en determinadas situaciones esta impedancia puede cambiar de valor y fluctuar como consecuencia de la interacción de la antena con el usuario y su entorno, lo que puede conducir a una reducción dramática de la eficiencia del PA. Además de la eficiencia, la linealidad puede verse también seriamente comprometida ante dichas variaciones de la carga. Para solventar, o de alguna manera mejorar estos problemas, hace ya unos cuantos años surgió el concepto de las redes de adaptación reconfigurables. Estos circuitos buscan la transformación de impedancias óptima que permita una transmisión de potencia, con las menores pérdidas posibles, entre la fuente y la carga, pero añadiendo la propiedad de la reconfigurabilidad, esto es, que mediante algún mecanismo de control electrónico y automático, las propiedades de adaptación de la red pueden cambiar, permitiéndole adaptarse a las condiciones del sistema. El objetivo final del uso de las redes de adaptación reconfigurables en sistemas de transmisión y/o recepción es la mejora de la eficiencia. En los últimos años se ha estudiado y verificado su utilidad en diversos contextos que van desde la mejora de la eficiencia en algunas arquitecturas de transmisión, la capacidad para mejorar condiciones de desadaptación en entornos variables, o la contribución a la reducción de componentes y mejora de la eficiencia en sistemas multi-modo y/o multi-banda. En esta tesis doctoral se van a tratar varios aspectos relacionados con el diseño, caracterización y aplicaciones de este tipo de dispositivos. En un principio, se partirá de una revisión del estado del arte en cuanto a tecnologías de radio frecuencia y redes de adaptación reconfigurables. Inicialmente se presentan las tecnologías más habituales para conseguir reconfigurabilidad en circuitos de RF, esencialmente, diodos PIN, varactores, transistores y MEMS (Micro-Electro-Mechanical System), analizando sus características fundamentales, ventajas, problemas y últimos desarrollos en el mercado. Posteriormente se presenta una revisión del estado del arte centrado en las redes de adaptación reconfigurables en diferentes tecnologías. El estudio y análisis de las figuras de mérito y medida de prestaciones para redes de adaptación reconfigurables constituirá una importante parte en la presente tesis. Utilizando un prototipo de referencia se presentan distintas métricas, discutiendo su viabilidad para medir de manera precisa las prestaciones de este tipo de redes. Una vez definidas las métricas, se presentan diversos diseños y prototipos en diferentes tecnologías, para después presentar un mecanismo de optimización y automatización para redes controladas digitalmente. Por último se estudian diversas aplicaciones de este tipo de redes en sistemas de transmisión y recepción de sistemas móviles. En cuanto a recepción, se presenta un estudio para mejorar la eficiencia general de sistemas basados en el estándar DVB-H. Utilizando redes de adaptación reconfigurables se verificará la mejora en la ganancia realizada en estos sistemas, además de contribuir a la mejora de la relación señal a ruido a la salida del amplificador de bajo ruido. En cuanto a los sistemas de transmisión se presentan diversos mecanismos para mejorar la eficiencia bajo condiciones de carga variable. Se propondrán varias soluciones tanto con el uso de combinadores resistivos como de combinadores no aislados en arquitecturas LINC. Para estos últimos, se presentará un mecanismo basado en un combinador Chireix ajustable que permitirá compensar hasta cierto punto las variaciones en la impedancia de carga. Posteriormente se presentará un sistema de modulación dinámica de carga usando redes de adaptación reconfigurables, y su aplicación para condiciones de carga variable. Finalmente se estudiará el uso de redes de adaptación reconfigurables para la mejora de la sensibilidad en la aplicación de técnicas de predistorsión digital

Receptores de rádio-frequência melhorados e disruptivos

This Ph.D. mainly addresses the reception part of a radio front end, focusing on Radio Frequency (RF) sampling architectures. These are considered to be the most promising future candidates to get better performance in terms of bandwidth and agility, following the well-known Software-Defined Radio (SDR) concept. The study considers the usage of an RF receiver in a standalone operation, i.e., used for receiving unknown data at the antenna, and when used as observation path for Power Amplifier (PA) linearization via Digital Predistortion (DPD), since nowadays this represents a mandatory technique to increase overall system’s performance. Firstly, commercial available RF Analog-Digital-Converters (ADCs) are studied and characterized to understand their limitations when used in DPD scenarios. A method for characterization and digital post-compensation to improve performance is proposed and evaluated. Secondly, an innovative FPGA-based RF single-bit pulsed converter based on Pulse Width Modulation (PWM) is addressed targeting frequency agility, high analog input bandwidth, and system integration, taking profit of an FPGA-based implementation. The latter was optimized based on PWM theoretical behavior maximizing Signal-to-Noise-Ratio (SNR) and bandwidth. The optimized receiver, was afterwards evaluated in a 5G C-RAN architecture and as a feedback loop for DPD. Finally, a brief study regarding DPD feedback loops in the scope of multiantenna transmitters is presented. This Ph.D. contributes with several advances to the state-of-the-art of SDR receiver, and to the so-called SDR DPD concept.Este doutoramento endereça principalmente a componente de receção de um transcetor de rádio-frequência (RF), focando-se em arquiteturas de receção de amostragem em RF. Estas são assim consideradas como sendo as mais promissoras para o futuro, em termos de desempenho, largura de banda e agilidade, de acordo com o conhecido conceito de Rádios Definidos por Software (SDR). O estudo considera o uso dos recetores de RF em modo standalone, i.e., recebendo dados desconhecidos provenientes da antena, e também quando usados como caminho de observação para aplicação de linearização de amplificadores de potência (PAs) via pré-distorção digital (DPD), pois atualmente esta é uma técnica fundamental para aumentar o desempenho geral do sistema. Em primeiro lugar, os conversores analógico-digital de RF são estudados e caracterizados para perceber as suas limitações quando usados em cenários de DPD. Um método de caracterização e pós compensação digital é proposto para obter melhorias de desempenho. Em segundo lugar, um novo recetor pulsado de um bit baseado em Modulação de Largura de Pulso (PWM) e implementado em Agregado de Células Lógicas Programáveis (FPGA) é endereçado, visando agilidade em frequência, largura de banda analógica e integração de sistema, tirando proveito da implementação em FPGA. Este recetor foi otimizado com base no modelo comportamental teórico da modulação PWM, maximizando a relação sinalruído (SNR) e a largura de banda. O recetor otimizado foi posteriormente avaliado num cenário 5G de uma arquitetura C-RAN e também num cenário em que serve de caminho de observação para DPD. Finalmente, um breve estudo relativo a caminhos de observação de DPD no contexto de transmissores multi-antena é também apresentado. Este doutoramento contribui com vários avanços no estado da arte de recetores SDR e no conceito de SDR DPD.Programa Doutoral em Engenharia Eletrotécnic

Imaging Sensors and Applications

In past decades, various sensor technologies have been used in all areas of our lives, thus improving our quality of life. In particular, imaging sensors have been widely applied in the development of various imaging approaches such as optical imaging, ultrasound imaging, X-ray imaging, and nuclear imaging, and contributed to achieve high sensitivity, miniaturization, and real-time imaging. These advanced image sensing technologies play an important role not only in the medical field but also in the industrial field. This Special Issue covers broad topics on imaging sensors and applications. The scope range of imaging sensors can be extended to novel imaging sensors and diverse imaging systems, including hardware and software advancements. Additionally, biomedical and nondestructive sensing applications are welcome