An off-line multiprocessor real-time scheduling algorithm to reduce static energy consumption

International audienceEnergy consumption of highly reliable real-time embedded systems is a significant concern. Static energy consumption tends to become more important than dynamic energy consumption. This paper aims to propose a new off-line scheduling algorithm to put as much as possible processors in low- power states instead of idling. In these states, energy consumption is reduced, enhancing the battery life-time of mission critical systems. However, no instruction can be executed and a transition delay is required to come back to the active state. Activating deeper low-power states requires to produce larger idle periods. As the processor usage is constant for a given task set, this objective implies reducing the number of idle periods. Our proposal is to modelize the processors idle time as an additional task. Then we formalize the problem as a linear equation system with the objective of reducing the number of preemptions (or executions) of this additional task. Simulations show that our algorithm is more energy efficient than existing algorithms

Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device

Dynamic power management has been adopted in many systems to reduce the power/energy consumption by changing the system state dynamically. This paper explores energy efficiency for systems equipped with PCI-Express devices, which are designed for low power consumption and high performance, compared to corresponding PCI devices. We propose dynamic power management mechanism and a management policy for energy-efficient considerations. A case study for a variable-bit-rate local-area-network device under the PCI-Express specification is exploited to provide supports for dynamic packet transmission. Simulation results show that the proposed mechanism and policy would reduce the system energy consumption substantiall

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

A hybrid genetic algorithm with mapreduce technique for cloud computing energy efficiency

Computer clouds generally comprise large power-consuming data centers as they are designed to support the elasticity and scalability required by customers. However, while cloud computing reduces energy consumption for customers, it is an issue for providers who have to deal with increasing demand and performance expectations. This creates the need for mechanisms to improve the energy-efficiency of cloud computing data centers while maintaining desired levels of performance. This research seeks to formulate a hybrid algorithm based on Genetic algorithm and MapReduce algorithm techniques to further promote energy efficiency in the cloud computing platform. The function of the MapReduce algorithm is to optimize scheduling performance which is one of the more efficient techniques for handling large data in servers. Genetic algorithm is effective in optimally measuring the value of operations and allows for the minimization of energy efficiency where it includes the formula for single optimization energy efficiency. A series of simulations were developed to evaluate the effectiveness of the proposed algorithm. The evaluation results show the amount of Information Technology equipment power required for Power Usage Effectiveness values to optimize energy usage where the performance of the proposed algorithm is 6% better than the previous genetic algorithm and 5% better than Hadoop MapReduce scheduling on low load conditions. On the other hand, the proposed algorithm improved energy efficiency in comparison with the previous work

Ordonnancement temps réel et minimisation de la consommation d'énergie

La consommation en énergie est devenue un problème crucial dans la conception des équipements électroniques dont l'alimentation est assurée par des batteries. Parmi tous les composants électroniques, le processeur est particulièrement utilisateurs d'énergie puisque des études ([POU 01, ZEN 02] cités dans [AYD 04]) ont montré qu'il pouvait à lui seul utiliser plus de 50 % de l'énergie lorsqu'il était sollicité intensivement. En jouant sur une réduction de la fréquence de fonctionnement du processeur, des stratégies d'ordonnancement adaptées permettent de réduire considérablement la consommation énergétique. Nous proposons dans ce chapitre un tour d'horizon, dans le cas mono-processeur, des techniques d'ordonnancement visant à minimiser la consommation d'énergie tout en garantissant le respect de contraintes d'échéances. Les contraintes de temps peuvent peser explicitement sur certaines activités du système ou peuvent provenir de contraintes de performances minimales si l'on sort du cadre classique des systèmes temps réel. Le problème d'ordonnancement à résoudre consiste non seulement à déterminer l'ordre dans lequel exécuter les activités du système mais également à fixer la fréquence de fonctionnement du processeur au cours du temps. Comme souligné dans [GRU 02], l'ordonnancement sous contrainte d'énergie acquiert une nouvelle dimension qui est la vitesse du processeur