Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Reducing cache hierarchy energy consumption by predicting forwarding and disabling associative sets

The first level data cache in modern processors has become a major consumer of energy due to its increasing size and high frequency access rate. In order to reduce this high energy consumption, we propose in this paper a straightforward filtering technique based on a highly accurate forwarding predictor. Specifically, a simple structure predicts whether a load instruction will obtain its corresponding data via forwarding from the load-store structure - thus avoiding the data cache access - or if it will be provided by the data cache. This mechanism manages to reduce the data cache energy consumption by an average of 21.5% with a negligible performance penalty of less than 0.1%. Furthermore, in this paper we focus on the cache static energy consumption too by disabling a portion of sets of the L2 associative cache. Overall, when merging both proposals, the combined L1 and L2 total energy consumption is reduced by an average of 29.2% with a performance penalty of just 0.25%

Chapter One – An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years. Both computer architects and circuit designers intent to reduce power and energy (without a performance degradation) at all design levels, as it is currently the main obstacle to continue with further scaling according to Moore's law. The aim of this survey is to provide a comprehensive overview of power- and energy-efficient “state-of-the-art” techniques. We classify techniques by component where they apply to, which is the most natural way from a designer point of view. We further divide the techniques by the component of power/energy they optimize (static or dynamic), covering in that way complete low-power design flow at the architectural level. At the end, we conclude that only a holistic approach that assumes optimizations at all design levels can lead to significant savings.Peer ReviewedPostprint (published version

Microarchitectural techniques to reduce energy consumption in the memory hierarchy

This thesis states that dynamic profiling of the memory reference stream can improve energy and performance in the memory hierarchy. The research presented in this theses provides multiple instances of using lightweight hardware structures to profile the memory reference stream. The objective of this research is to develop microarchitectural techniques to reduce energy consumption at different levels of the memory hierarchy. Several simple and implementable techniques were developed as a part of this research. One of the techniques identifies and eliminates redundant refresh operations in DRAM and reduces DRAM refresh power. Another, reduces leakage energy in L2 and higher level caches for multiprocessor systems. The emphasis of this research has been to develop several techniques of obtaining energy savings in caches using a simple hardware structure called the counting Bloom filter (CBF). CBFs have been used to predict L2 cache misses and obtain energy savings by not accessing the L2 cache on a predicted miss. A simple extension of this technique allows CBFs to do way-estimation of set associative caches to reduce energy in cache lookups. Another technique using CBFs track addresses in a Virtual Cache and reduce false synonym lookups. Finally this thesis presents a technique to reduce dynamic power consumption in level one caches using significance compression. The significant energy and performance improvements demonstrated by the techniques presented in this thesis suggest that this work will be of great value for designing memory hierarchies of future computing platforms.Ph.D.Committee Chair: Lee, Hsien-Hsin S.; Committee Member: Cahtterjee,Abhijit; Committee Member: Mukhopadhyay, Saibal; Committee Member: Pande, Santosh; Committee Member: Yalamanchili, Sudhaka

Unilateral Climate Policy, Asymmetric Backstop Adoption, and Carbon Leakage in a Two-Region Hotelling Model

We study backstop adoption and carbon dioxide emission paths in a two-region model with unilateral climate policy and non-renewable resource consumption. The regions have an equal endowment of the internationally tradable resource and a backstop technology. We first study the case of a unilateral stock constraint (e.g. a 450 ppmv carbon dioxide concentration target), and show that the non-abating region makes the final switch to the backstop before the abating region does, though the latter region has two disjoint phases of backstop use if its marginal cost is sufficiently low. Furthermore, we show that the abating region has an inverse N-shaped emission path, with growing emissions in the period for which the ceiling is binding. In addition, there is a phase in which this region has a positive carbon price, but higher emissions than the non-abating region. With a global intertemporal carbon budget instead of a stock constraint, the order of definite backstop adoption is reversed and the abating region’s emissions are always lower. We also show that unilateral climate policy does not lead to international carbon leakage.climate policy, non-renewable resources, backstop technology, carbon leakage, unilateral climate policy

A low-power cache system for high-performance processors

制度:新 ; 報告番号:甲3439号 ; 学位の種類:博士(工学) ; 授与年月日:12-Sep-11 ; 早大学位記番号:新576

A Global Meta-Analysis of Forest Bioenergy Greenhouse Gas Emission Accounting Studies

The potential greenhouse gas benefits of displacing fossil energy with biofuels are driving policy development in the absence of complete information. The potential carbon neutrality of forest biomass is a source of considerable scientific debate because of the complexity of dynamic forest ecosystems, varied feedstock types, and multiple energy production pathways. The lack of scientific consensus leaves decision makers struggling with contradicting technical advice. Analyzing previously published studies, our goal was to identify and prioritize those attributes of bioenergy greenhouse gas (GHG) emissions analysis that are most influential on length of carbon payback period. We investigated outcomes of 59 previously published forest biomass greenhouse gas emissions research studies published between 1991 and 2014. We identified attributes for each study and classified study cases by attributes. Using classification and regression tree analysis, we identified those attributes that are strong predictors of carbon payback period (e.g. the time required by the forest to recover through sequestration the carbon dioxide from biomass combusted for energy). The inclusion of wildfire dynamics proved to be the most influential in determining carbon payback period length compared to other factors such as feedstock type, baseline choice, and the incorporation of leakage calculations. Additionally, we demonstrate that evaluation criteria consistency is required to facilitate equitable comparison between projects. For carbon payback period calculations to provide operational insights to decision makers, future research should focus on creating common accounting principles for the most influential fac

Characterization of triboelectric charging in data centers/display panel manufactures, and EMI visualization based on energy parcels method in high speed interconnections

This dissertation is composed of five papers. In the first three papers, triboelectric charging, which is the underlying cause of most electrostatic discharge (ESD), during daily human activities in data centers such as well-defined pattern walking, random walking, standing up from a chair, and taking off a sweater is investigated. Further, the effect of environmental condition (temperature and relative humidity), the footwear, and flooring material in building the static voltage and the discharge process are studied. In the fourth paper, triboelectric charge generation on the glass is investigated during the glass transportation by roller conveyor systems in display manufacturing. The underlying parameters that affect the static charging on both glass and rollers consisting of roller material, roller radius, transfer velocity, transfer acceleration, traveling distance, and relative humidity are explored. The fifth paper focuses on the shielding effectiveness (SE) of quad form-factor pluggable (QSFP) interconnections cages with heatsinks, which are often only optimized for thermal, mechanical, and volume manufacturing. Energy parcels and their trajectory concept are applied to electromagnetic waves (EM) to visualize the coupling paths in a QSFP cage with a rising heatsink. The rising heatsink creates a new coupling path for EM waves to leak to the cage and emit from the routers/switches chassis faceplate. An EMI mitigation technique is introduced and its performance is evaluated with SE measurement for the frequency of 1-40 GHz with and without the active operational of 40 Gbps optical module in a dual reverberation chamber --Abstract, page iv

高電力効率プロセッサのためのキャッシュの設計最適化

学位の種別: 課程博士審査委員会委員 : （主査）東京大学教授 中村 宏, 東京大学教授 原 辰次, 東京大学教授 石川 正俊, 東京大学准教授 近藤 正章, 東京大学准教授 品川 高廣, 東京大学准教授 入江 英嗣University of Tokyo(東京大学

Dynamic cache reconfiguration based techniques for improving cache energy efficiency

Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this research, we propose novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. We propose software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with the state-of-art techniques and have found that our techniques outperform them in their energy efficiency. This research has important applications in improving energy-efficiency of higher-end embedded, desktop, server processors and multitasking systems. We have also proposed performance estimation approach for efficient design space exploration and have implemented time-sampling based simulation acceleration approach for full-system architectural simulators.Comment: PhD thesis, dynamic cache reconfiguratio