制度:新 ; 報告番号:甲3439号 ; 学位の種類:博士(工学) ; 授与年月日:12-Sep-11 ; 早大学位記番号:新576

Ye Jiongyao

English

制度:新 ; 報告番号:甲3439号 ; 学位の種類:博士(工学) ; 授与年月日:12-Sep-11 ; 早大学位記番号:新5763textthesi

Ye, Jiongyao

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Waseda University Repository

A low-power cache system for high-performance processors

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早稲田大学大学院情報生産システム研究科博 士 論 文 概 要論 文 題 目A Lo w-po w e r Ca che Sys te m fo rH ig h -pe r f o rman ce Pro ce sso r s申 請 者YE, Jiongyao情報生産システム工学専攻ASIC自動設計研究2011 年 09 月2In modern processors , a cache sys tem becomes the main contr ibutor ofthe tota l power consumption as i t great ly improves the performance . Mostof the power consumpt ion is caused by i ts complex arch i tecture , veryfrequent access and progress ive ly increased s ize . This thes i s presentsthree techniques in a cache sys tem in order to reduce both powerconsumpt ion and access latency. We also propose a nove l recoverymechanism, which uses a spec ia l cache to e l iminate the per formancedegradat ion due to our proposed opt imizat ion.In Chapter 1, we f i rs t rev iew the pr inc ip le of cache and two popularcache archi tec tures . Then, we analyzed the cache access t ime and energy.Based on these theoret ica l foundat ions and analys is , we survey thecurrent mains tream techniques on high-speed and low-power cachedes igns . These techniques improve the per formance or reduce the powerconsumpt ion at many leve ls , such as devi ce leve l , c i rcu it l eve l , and so on.By re ferr ing to and deve lop ing the prev ious techniques , we propose fourapproaches in the next chapters , cons ider ing both per formance and powerconsumpt ion of cache.In Chapter 2 , we f ir s t propose a low-power Data Cache (D-Cache ) des ign,ca l l ed Adapt ive Var ious-width Data Cache (AVDC) . Our proposedmechanism exp lo i ts the va lue loca l i ty to reduce the s tat i c powerconsumpt ion and dynamic power consumpt ion of D-Cache . There is acommon understanding such as many values in a processor rare ly need thefu l l -b i t dynamic range suppor ted by a cache. The narrow-width valueoccup ies a large por t ion o f the cache access and storage . From the view ofth is observat ion, AVDC explo i ts the popular i ty o f narrow-width values toreduce the power consumpt ion o f D-Cache without performancedegradat ion . The data storage unit in AVDC cons is ts of three sub-arraysto store data wi th d i f f erent widths . When the high sub-arrays are notused, the modi f i ed high-b i t SRAM cel l s can be c losed to save the i rdynamic and stat i c power consumpt ion. The main advantages o f AVDC are:1) Both the dynamic and stat i c power consumpt ion can be reduced. 2) Lowpower consumpt ion is achieved by the modi f i cat ion of the data s torageunit with less hardware modi f i cat ion. 3) We exp lo i t the redundancy ofnarrow-width values instead of compressed values , thus cache accesslatency does not increase . Exper imenta l resu lt s us ing SPEC 2000benchmarks show that our proposed AVDC can reduce the powerconsumpt ion, by 34.83% for dynamic power and by 42.87% for stat ic poweron average , compared with a trad it i ona l D-Cache.3In Chapter 3, as the second technique, we present a new power-awareIns truc t ion Fetch Uni t ( IFU) archi tecture , named Analys i s Before Start ingan Access (ABSA) , which a ims at maximiz ing the power e f f i c i ency of thelow-power techniques on Instruct ion Cache ( I -Cache ) by el iminat ing therest r ic t ions on those low-power techniques in the trad i t iona l IFU. Toachieve this goa l , ABSA reorganizes the IFU pipe l ine and care fu l lyass igns tasks for each s tage so that suf f i c i ent t ime and informat ion can beprov ided for the low-power techniques to maximize the power ef f i c iencybefore s tar t ing an access . The proposed des ign is fu l ly scalab le and thecost is l ow. Compared to a convent ional IFU des igns , s imulat ion result sshow that ABSA saves about 30 .3% fetch power consumption, on average .I -Cache employed by ABSA reduces both stat ic and dynamic powerconsumpt ions about 85 .63% and 66.92%, respec t ive ly. Meanwhi le theperformance degradat ion is only about 0.97%. However, an obviousprob lem of ABSA is the per formance degradat ion because the branchmispred ic t ion penalty is increased by lengthening the pipel ine stages .To address th is problem, we fur ther propose a new recovery mechanism,ca l l ed Cr i t i ca l Recovery Trace Cache (CRTC) in Chapter 4. This proposedCRTC can reduce the penal ty o f branch mispred i ct i on recovery that isampl i f ied by our proposed ABSA approach. The mechanism employs acr i t i ca l path predi ctor to ident i fy the branches that wi l l be most harmfuli f mispred ic ted . Once the branch is ident i f i ed as cr i t i ca l , a set ofsuccess ive decoded inst ruc t ions fo l lowing i t are saved into a smal ls impl i f i ed trace cache . Then during subsequent pred i ct i on, the CRTC isaccessed . I f there is a hi t , the ins t ruct ions f rom the alternat ive path canbe fed to rename stage immediate ly af ter a mispred i ct i on detec ted . Thus ,the re - f i l l la tency o f f et ch and decode s tages are ef f i c i ent ly reduced . Theexper imenta l resu lt s employ ing SPEC 2000 benchmark show that theproposed CRTC can improve Ins truct ion Per Cyc le ( IPC) va lue by4.8% on average , compared with a convent ional processor without CRTC.Final ly, in Chapter 5 , we introduce another advanced cache technique toreduce the power consumpt ion of a cache. So far, our proposed low-powertechniques on a cache are based on a f ixed hardware conf igurat ion, whichare not adaptable and depending on the program behaviors . We fur therpropose to employ the reconf igurab le technique to save energy with l i t t l e4performance degradat ion by dynamica l ly ad just ing the cache parametersfor the code that i s execut ing . However, the ex is t ing reconf igurable cacheexp lores and adapts the cache conf igurat ion based on a sequent ialinterval in t ime, which presents h igh e f f i c i ency only i f the program cankeep i ts execut ion phase for a number o f interva ls . We propose abehavior-based adapt ive cache , which can be dynamica l ly ad jus ted basedon the behavior of a program. The des ign adds very l i t t le hardwarecomplex ity and commits most work load to the sof tware so that i t is veryef fec t ive for the embedded microprocessors des ign. S imulat ion by us ingSpec 2000 shows that our proposed reconf igurab le cache can reduce thepower consumption by up to 63% and 22% compared to a convent iona lse t -assoc iat ive cache and an interva l -based reconf igurab le cache,respect ive ly. At the same t ime, per formance is improved by 4.8% and0.76%, respect ive ly.In conc lus ion, we summarize th is thes is i s s tud ies o f a cache sys tem toachieve the high-per formance and low-power processors . We accompl i shth is purpose in four d i f ferent ways . The f i rs t method reduces powerconsumpt ion and access latency o f a cache by modi fy ing the c ir cu it o fSRAM array. The second method focuses on the opt imizat ion o f a processorpipel ine to remove the res tr i c t i ons on the low-power techniques o f atradi t iona l micro -arch itecture . The th i rd way is to d i rec t ly use a smal l ,spec ia l ‘ cache ’ t o not only reduce the branch mispredi ct i on penal ty buta lso the power consumpt ion caused by re f i l l ing the p ipel ine af ter amispred ic t ion . This mechanism is the complement to the ABSA. In the last ,we presents a new cache technique to reduce the power consumpt ion b ydynamica l ly adapt ing the cache conf igurat ion . The las t way is adapt ive toboth D-Cache and I-Cache. The exper imenta l resu lt s show that theproposed approaches save the power consumpt ion and reduce the accesslatency compared to the convent iona l cache des ign. The results al so showthe proposed des igns have exce l lent sca lab i l i ty.

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A low-power cache system for high-performance processors

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