Compact Model for Flexible Ion-Sensitive Field-Effect Transistor

This paper presents the theoretical modelling, and simulation of bending effects on an ion-sensitive field-effect transistor (ISFET), towards futuristic bendable integrated circuits and microsystems for biomedical applications. Based on variations of threshold voltage and drain current under different bending conditions and orientations of the channel of the device, the bendable ISFET macro-model has been implemented in Verilog-A, and compiled into the Cadence environment. The effects of bending on the behaviour of the device have been simulated over a user-defined range of pH, and sensitivities in a standard 0.18-μm CMOS technology. It has been found that the transfer curves (Id-Vg) of ISFET vary up to 4.46% for tensile and up to 5.15% for compressive bending stress at pH 2, and up to 4.99% for tensile and 5.61% for compressive bending stress at pH 12 with respect to its planar counterpart, while the sensitivity of the device has been found to remain the same irrespectively of the bending stress. The proposed model has been validated by comparing the results with those obtained by other macro-models and experimental results in literature

Projeto de um oscilador integrado de 4 fases para aplicação em filtros passa banda de faixa estreita em tecnologia FD-SOI 22 nm

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2022.O presente trabalho apresenta a análise e o projeto de um oscilador em anel totalmente integrado de saída diferencial para aplicações em filtros de banda estreita. O oscilador foi projetado integralmente na tecnologia 22 nm FD-SOI da GlobalFoundries. O projeto dos blocos e a integração entre oscilador e filtro são feitos em nível de esquemático e leiaute. A fim de reduzir o consumo, a tensão de alimentação é de 500 mV. O núcleo do oscilador é polarizado em corrente que varia entre 7,8 uA até 30,5 uA para operar na faixa de frequência de 800 MHz até 2,4 GHz. O oscilador é composto de 3 blocos, sendo eles o núcleo, o deslocador de nível (level-shifter), e o buffer de saída. As simulações de corners e Monte Carlo mostram que a frequência de oscilação pode ser mantida dentro da faixa desejada através de ajuste na corrente de polarização do oscilador, mesmo que esse opere dentro de uma faixa de temperatura entre 0 e 80 graus Celsius, tanto no nível de esquemático quanto no nível de leiaute. A conexão do oscilador com um filtro faixa estreita 4-path sintonizado em 1 GHz resultou em largura de banda de 4 MHz e 20 dB de atenuação na faixa de rejeição. O consumo de potência a 1 GHz é de 25,5 uW, enquanto a 2,4 GHz é de 57,5 uW.Abstract: This work presents the analysis and design of a fully integrated differential output ring oscillator for application in narrowband filter. The oscillator is designed entirely on GlobalFoundries 22 nm FD-SOI technology. The design of the blocks and the integration between oscillator and filter are done at the schematic and layout level. In order to reduce consumption, the supply voltage is 500 mV. The oscillator core is biased from a current source ranging from 7.8 uA to 30.5 uA to operate in the frequency range from 800 MHz to 2.4 GHz. The oscillator is composed of 3 blocks, namely the core, the level shifter, and the output buffer. Corners and Monte Carlo simulations at the schematic and layout levels show that the oscillation frequency can be kept within the desired range by adjusting the oscillator's bias current, even if it operates within a temperature range between 0 and 80 degrees Celsius, both at the level schematic and layout level. Connecting the oscillator to a 4-path narrowband filter tuned to 1 GHz resulted in 4 MHz bandwidth and 20 dB attenuation in the stop band. The power consumption at 1 GHz is 25.5 uW, while at 2.4 GHz it is 57.5 uW

저 잡음 디지털 위상동기루프의 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 정덕균.As a device scaling proceeds, Charge Pump PLL has been confronted by many design challenges. Especially, a leakage current in loop filter and reduced dynamic range due to a lower operating voltage make it difficult to adopt a conventional analog PLL architecture for a highly scaled technology. To solve these issues, All Digital PLL (ADPLL) has been widely studied recently. ADPLL mitigates a filter leakage and a reduced dynamic range issues by replacing the analog circuits with digital ones. However, it is still difficult to get a low jitter under low supply voltage. In this thesis, we propose a dual loop architecture to achieve a low jitter even with a low supply voltage. And bottom-up based multi-step TDC and DCO are proposed to meet both fine resolution and wide operation range. In the aspect of design methodology, ADPLL has relied on a full custom design method although ADPLL is fully described in HDL (Hardware Description Language). We propose a new cell based layout technique to automatically synthesize the whole circuit and layout. The test chip has no linearity degradation although it is fully synthesized using a commercially available auto P&R tool. We has implemented an all digital pixel clock generator using the proposed dual loop architecture and the cell based layout technique. The entire circuit is automatically synthesized using 28nm CMOS technology. And s-domain linear model is utilized to optimize the jitter of the dual-loop PLL. Test chip occupies 0.032mm2, and achieves a 15ps_rms integrated jitter although it has extremely low input reference clock of 100 kHz. The whole circuit operates at 1.0V and consumes only 3.1mW.Abstract i Lists of Figures vii Lists of Tables xiii 1. Introduction 1 1.1 Thesis Motivation and Organization 1 1.1.1 Motivation 1 1.1.2 Thesis Organization 2 1.2 PLL Design Issues in Scaled CMOS Technology 3 1.2.1 Low Supply Voltage 4 1.2.2 High Leakage Current 6 1.2.3 Device Reliability: NBTI, HCI, TDDB, EM 8 1.2.4 Mismatch due to Proximity Effects: WPE, STI 11 1.3 Overview of Clock Synthesizers 14 1.3.1 Dual Voltage Charge Pump PLL 14 1.3.2 DLL Based Edge Combining Clock Multiplier 16 1.3.3 Recirculation DLL 17 1.3.4 Reference Injected PLL 18 1.3.5 All Digital PLL 19 1.3.6 Flying Adder Clock Synthesizer 20 1.3.7 Dual Loop Hybrid PLL 21 1.3.8 Comparisons 23 2. Tutorial of ADPLL Design 25 2.1 Introduction 25 2.1.1 Motivation for a pure digital 25 2.1.2 Conversion to digital domain 26 2.2 Functional Blocks 26 2.2.1 TDC, and PFD/Charge Pump 26 2.2.2 Digital Loop Filter and Analog R/C Loop Filter 29 2.2.3 DCO and VCO 34 2.2.4 S-domain Model of the Whole Loop 34 2.2.5 ADPLL Loop Design Flow 36 2.3 S-domain Noise Model 41 2.3.1 Noise Transfer Functions 41 2.3.2 Quantization Noise due to Limited TDC Resolution 45 2.3.3 Quantization Noise due to Divider ΔΣ Noise 46 2.3.4 Quantization Noise due to Limited DCO Resolution 47 2.3.5 Quantization Noise due to DCO ΔΣ Dithering 48 2.3.6 Random Noise of DCO and Input Clock 50 2.3.7 Over-all Phase Noise 50 3. Synthesizable All Digital Pixel Clock PLL Design 53 3.1 Overview 53 3.1.1 Introduction of Pixel Clock PLL 53 3.1.1 Design Specifications 55 3.2 Proposed Architecture 60 3.2.1 All Digital Dual Loop PLL 60 3.2.2 2-step controlled TDC 61 3.2.3 3-step controlled DCO 64 3.2.4 Digital Loop Filter 76 3.3 S-domain Noise Model 78 3.4 Loop Parameter Optimization Based on the s-domain Model 85 3.5 RTL and Gate Level Circuit Design 88 3.5.1 Overview of the design flow 88 3.5.2 Behavioral Simulation and Gate level synthesis 89 3.5.1 Preventing a meta-stability 90 3.5.1 Reusable Coding Style 92 3.6 Layout Synthesis 94 3.6.1 Auto P&R 94 3.6.2 Design of Unit Cells 97 3.6.3 Linearity Degradation in Synthesized TDC 98 3.6.4 Linearity Degradation in Synthesized DCO 106 3.7 Experiment Results 109 3.7.1 DCO measurement 109 3.7.2 PLL measurement 113 3.8 Conclusions 117 A. Device Technology Scaling Trends 118 A.1. Motivation for Technology Scaling 118 A.2. Constant Field Scaling 120 A.3. Quasi Constant Voltage Scaling 123 A.4. Device Technology Trends in Real World 124 B. Spice Simulation Tip for a DCO 137 C. Phase Noise to Jitter Conversion 141 Bibliography 144 초록 151Docto

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Diseño de circuitos electrónicos de ultra-bajo consumo en tecnologías nanométricas

El escalado de los procesos de fabricación de semiconductores, predicho por el Dr. Moore en los años sesenta, ha tenido un gran impacto en el desarrollo de la electrónica integrada actual. Por una parte, la reducción del tamaño de los transistores ha permitido incrementar la densidad de integración, dando la posibilidad a los diseñadores de introducir un mayor número de funcionalidades dentro de una misma área. Por otro lado, este fenómeno ha llevado consigo una reducción de los costes asociados a la fabricación, logrando abaratar el producto final. Esta continua evolución e incremento de la funcionalidad dentro de un mismo circuito integrado, implica, a su vez, un aumento de la complejidad a la hora de planificar la generación y distribución de las distintas tensiones de alimentación, necesarias para cada uno de los bloques incluidos en el chip. Esto provoca que las especificaciones de ruido, regulación y/o estabilidad asociadas a cada dominio de alimentación varíen según la naturaleza del sistema al que se pretende alimentar. Por esta razón, los circuitos destinados a la gestión de la potencia han tomado una mayor relevancia en los últimos años, puesto que las restricciones impuestas por los sistemas integrados son cada vez mayores. Dentro de los circuitos destinados a la gestión de potencia, los reguladores lineales y, en concreto, los de bajo dropout se corresponden con un bloque básico, ya que permiten la generación de tensiones de alimentación muy estables, precisas y de bajo ruido. Estas características los convierten en el circuito ideal para alimentar a sistemas analógicos o de radio-frecuencia, muy sensibles a variaciones de la alimentación. Otra característica de estos bloques, que ha provocado el creciente interés de la comunidad científica en ellos, es la posibilidad de poder integrarlos sin necesidad de incluir ningún dispositivo externo, con el consecuente ahorro económico y de área en la tarjeta impresa. Sin embargo, dentro de los inconvenientes cabe destacar dos. Por una parte, la eficiencia máxima teórica que pueden lograr es baja frente a soluciones basadas en capacidades conmutadas o inductores. Por otro lado, al buscarse un esquema de compensación interna, el polo dominante del sistema viene fijado por un nodo interno del circuito, provocando que el polo no-dominante esté dominado por la carga. Esto se traduce en un gran problema de estabilidad, debido a que las variaciones que sufre la carga se traducen en un desplazamiento en frecuencia del polo no dominante, degradando el margen de fase de todo el sistema. Según lo descrito anteriormente, esta investigación se ha centrado en el estudio de reguladores lineales de tipo Low-DropOut o LDO compensados internamente y sus propiedades, dada la problemática de este tipo de celdas cuando se busca minimizar su consumo quiescente. Para ello, uno de los objetivos marcados versa sobre la búsqueda de topologías alternativas que permitan el diseño de LDOs de altas prestaciones, sin suponer un incremento del consumo quiescente y que sean válidos para entornos de baja tensión de alimentación. En este sentido, se ha apostado por el uso de la celda Flipped Voltage Follower como regulador debido a su baja impendancia de salida, gran estabilidad y sencillez. Una segunda línea, se ha centrado en la búsqueda de esquemas de compensación simples que permitan extender la estabilidad de este tipo de regulador en todo el rango de funcionamiento. Para ello, se ha explorado un esquema basado en la compensación clásica de Miller donde se ha utilizado un esquema de replica para ajustar de forma dinámica el valor de la resistencia según la carga del sistema. Por último, con el objetivo de minimizar lo máximo posible el consumo quiescente de los reguladores LDOs sin degradar las prestaciones de la respuesta transitoria, se ha explorado el uso de buffers clase AB para gestionar la puerta del transistor de paso. Esta técnica permite mejorar la respuesta transitoria, al ser capaz de crear corrientes elevadas durante las transiciones sin necesidad de penalizar la eficiencia del regulador.The continuous downscaling of semiconductor fabrication processes, which was predicted by PhD. Moore in 1965, have had a great impact in the development of nowadays integrated electronics. The reduction of transistor size has allowed, on one hand, the integration of more devices in the same área, increasing the integration density, while, on the other hand, has led to the reduction of fabrication costs, making the final product cheaper and accessible. However, this increase in the functionality of a single integrated circuit entails greater complexity in the generation and distribution of the different biasing voltages needed throughout one chip. Thus, as more different systems are integrated in the same chip, more different biasing domains coexists in it, leading several different requirements of noise, regulation and/or stability that need to be satisfied simultaneously. Therefore, power management circuits have been acquiring greater significance as technology downscales, reaching its maximum nowadays, when the nanoscale had taken those issues to its culmen. Linear regulators, and more concretely, low-dropout linear regulators, are an essential block in any power management system, able to generate precise and extremely-stable low-noise biasing voltages what make them the ideal choice for extremely biasing-sensitive circuits such as analog or radio-frequency systems. In addition to this, low-dropout linear regulators can be completely integrated without needing any external device, what translates to expenses and area savings. For all these reasons, low-dropout linear regulators have been lately acquiring extensive attention from the scientific community. However, those circuits also have some disadvantages, indeed, the maximum theoretical efficiency that can be achieved though low-dropout linear regulators is lower than switched capacitor or inductor-based solutions efficiency. In addition to this, as internal compensation is required, the system’s dominant pole is given by an internal node, making the non-dominant pole to be fixed by the charge. This leads to a great stability concern as charge variations translate to a frequency displacement of the non-dominant pole that degrades the whole system phase margin. In accordance with previously described issues, this research has been focused on the study of minimum-quiescent consumption internally compensated low-dropout linear regulators (LDO). The first objective of this research is the proposal of low-voltage high-performance LDO structures that do not increase quiescent consumption. Thus, the Flipped Voltage Follower cell has been proposed as regulator due to its inherent low output impedance, great stability and simplicity. The second aim of this research has been the proposal of simple compensation schemes that allow full-operation range stability. So that, a classical Miller compensation based scheme where a replica circuit dynamically adjust the charge resistance has been proposed. Finally, in order to minimize quiescent consumption of LDOs regulators without degrading transient response performance, class-AB buffers have been proposed to drive the pass transistor gate. This technique enhances the transient response as it generates high currents during transitions without compromising efficiency.Premio Extraordinario de Doctorado U

Variability-Aware Circuit Performance Optimisation Through Digital Reconfiguration

This thesis proposes optimisation methods for improving the performance of circuits imple- mented on a custom reconfigurable hardware platform with knowledge of intrinsic variations, through the use of digital reconfiguration. With the continuing trend of transistor shrinking, stochastic variations become first order effects, posing a significant challenge for device reliability. Traditional device models tend to be too conservative, as the margins are greatly increased to account for these variations. Variation-aware optimisation methods are then required to reduce the performance spread caused by these substrate variations. The Programmable Analogue and Digital Array (PAnDA) is a reconfigurable hardware plat- form which combines the traditional architecture of a Field Programmable Gate Array (FPGA) with the concept of configurable transistor widths, and is used in this thesis as a platform on which variability-aware circuits can be implemented. A model of the PAnDA architecture is designed to allow for rapid prototyping of devices, making the study of the effects of intrinsic variability on circuit performance – which re- quires expensive statistical simulations – feasible. This is achieved by means of importing statistically-enhanced transistor performance data from RandomSPICE simulations into a model of the PAnDA architecture implemented in hardware. Digital reconfiguration is then used to explore the hardware resources available for performance optimisation. A bio-inspired optimisation algorithm is used to explore the large solution space more efficiently. Results from test circuits suggest that variation-aware optimisation can provide a significant reduction in the spread of the distribution of performance across various instances of circuits, as well as an increase in performance for each. Even if transistor geometry flexibility is not available, as is the case of traditional architectures, it is still possible to make use of the substrate variations to reduce spread and increase performance by means of function relocation

Regular cell design approach considering lithography-induced process variations

The deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced process variations. The effect of the lithography gap in current and upcoming technologies is to cause severe distortions due to optical diffraction in the printed patterns and thus degrading manufacturing yield. Therefore, a paradigm shift in layout design is mandatory towards more regular litho-friendly cell designs in order to improve line pattern resolution. However, it is still unclear the amount of layout regularity that can be introduced and how to measure the benefits and weaknesses of regular layouts. This dissertation is focused on searching the degree of layout regularity necessary to combat lithography variability and outperform the layout quality of a design. The main contributions that have been addressed to accomplish this objective are: (1) the definition of several layout design guidelines to mitigate lithography variability; (2) the proposal of a parametric yield estimation model to evaluate the lithography impact on layout design; (3) the development of a global Layout Quality Metric (LQM) including a Regularity Metric (RM) to capture the degree of layout regularity of a layout implementation and; (4) the creation of different layout architectures exploiting the benefits of layout regularity to outperform line-pattern resolution, referred as Adaptive Lithography Aware Regular Cell Designs (ALARCs). The first part of this thesis provides several regular layout design guidelines derived from lithography simulations so that several important lithography related variation sources are minimized. Moreover, a design level methodology, referred as gate biasing, is proposed to overcome systematic layout dependent variations, across-field variations and the non-rectilinear gate effect (NRG) applied to regular fabrics by properly configuring the drawn transistor channel length. The second part of this dissertation proposes a lithography yield estimation model to predict the amount of lithography distortion expected in a printed layout due to lithography hotspots with a reduced set of lithography simulations. An efficient lithography hotspot framework to identify the different layout pattern configurations, simplify them to ease the pattern analysis and classify them according to the lithography degradation predicted using lithography simulations is presented. The yield model is calibrated with delay measurements of a reduced set of identical test circuits implemented in a CMOS 40nm technology and thus actual silicon data is utilized to obtain a more realistic yield estimation. The third part of this thesis presents a configurable Layout Quality Metric (LQM) that considering several layout aspects provides a global evaluation of a layout design with a single score. The LQM can be leveraged by assigning different weights to each evaluation metric or by modifying the parameters under analysis. The LQM is here configured following two different set of partial metrics. Note that the LQM provides a regularity metric (RM) in order to capture the degree of layout regularity applied in a layout design. Lastly, this thesis presents different ALARC designs for a 40nm technology using different degrees of layout regularity and different area overheads. The quality of the gridded regular templates is demonstrated by automatically creating a library containing 266 cells including combinational and sequential cells and synthesizing several ITC'99 benchmark circuits. Note that the regular cell libraries only presents a 9\% area penalty compared to the 2D standard cell designs used for comparison and thus providing area competitive designs. The layout evaluation of benchmark circuits considering the LQM shows that regular layouts can outperform other 2D standard cell designs depending on the layout implementation.Los continuos retrasos en la implementación de la EUVL, fuerzan que el diseño de IC se realice mediante litografía de longitud de onda de 193 nm con innovadoras y costosas técnicas para poder combatir variaciones de proceso de litografía. La gran diferencia entre la longitud de onda y el tamaño de los patrones causa severas distorsiones debido a la difracción óptica en los patrones impresos y por lo tanto degradando el yield. En consecuencia, es necesario realizar un cambio en el diseño de layouts hacia diseños más regulares para poder mejorar la resolución de los patrones. Sin embargo, todavía no está claro el grado de regularidad que se debe introducir y como medir los beneficios y los perjuicios de los diseños regulares. El objetivo de esta tesis es buscar el grado de regularidad necesario para combatir las variaciones de litografía y mejorar la calidad del layout de un diseño. Las principales contribuciones para conseguirlo son: (1) la definición de diversas reglas de diseño de layout para mitigar las variaciones de litografía; (2) la propuesta de un modelo para estimar el yield paramétrico y así evaluar el impacto de la litografía en el diseño de layout; (3) el diseño de una métrica para analizar la calidad de un layout (LQM) incluyendo una métrica para capturar el grado de regularidad de un diseño (RM) y; (4) la creación de diferentes tipos de layout explotando los beneficios de la regularidad, referidos como Adaptative Lithography Aware Regular Cell Designs (ALARCs). La primera parte de la tesis, propone las diversas reglas de diseño para layouts regulares derivadas de simulaciones de litografía de tal manera que las fuentes de variación de litografía son minimizadas. Además, se propone una metodología de diseño para layouts regulares, referida como "gate biasing" para contrarrestar las variaciones sistemáticas dependientes del layout, las variaciones en la ventana de proceso del sistema litográfico y el efecto de puerta no rectilínea para configurar la longitud del canal del transistor correctamente. La segunda parte de la tesis, detalla el modelo de estimación del yield de litografía para predecir mediante un número reducido de simulaciones de litografía la cantidad de distorsión que se espera en un layout impreso debida a "hotspots". Se propone una eficiente metodología que identifica los distintos patrones de un layout, los simplifica para facilitar el análisis de los patrones y los clasifica en relación a la degradación predecida mediante simulaciones de litografía. El modelo de yield se calibra utilizando medidas de tiempo de un número reducido de idénticos circuitos de test implementados en una tecnología CMOS de 40nm y de esta manera, se utilizan datos de silicio para obtener una estimación realista del yield. La tercera parte de este trabajo, presenta una métrica para medir la calidad del layout (LQM), que considera diversos aspectos para dar una evaluación global de un diseño mediante un único valor. La LQM puede ajustarse mediante la asignación de diferentes pesos para cada métrica de evaluación o modificando los parámetros analizados. La LQM se configura mediante dos conjuntos de medidas diferentes. Además, ésta incluye una métrica de regularidad (RM) para capturar el grado de regularidad que se aplica en un diseño. Finalmente, esta disertación presenta los distintos diseños ALARC para una tecnología de 40nm utilizando diversos grados de regularidad y diferentes impactos en área. La calidad de estos diseños se demuestra creando automáticamente una librería de 266 celdas incluyendo celdas combinacionales y secuenciales y, sintetizando diversos circuitos ITC'99. Las librerías regulares solo presentan un 9% de impacto en área comparado con diseños de celdas estándar 2D y por tanto proponiendo diseños competitivos en área. La evaluación de los circuitos considerando la LQM muestra que los diseños regulares pueden mejorar otros diseños 2D dependiendo de la implementación del layout