ハードウェアリソースの高稼働率化に基づく細粒度多値リコンフィギャラブルVLSIアーキテクチャ

Tohoku University亀山充隆課

Design techniques for high-performance current-steering digital-to-analog converters

Digital-to-Analog Converter (DAC) is a crucial building block limiting the accuracy and speed of many signal processing and telecommunication systems. To achieve high speed and high resolution, the current-steering architecture is almost exclusively used. Three important issues for current-steering DAC design are addressed in this dissertation. In a current-steering DAC design, it is essential that a designer determine the minimum required current source accuracy to overcome random current mismatch and achieve high linearity with guaranteed yield. Simple formulas are derived that clearly exhibit the relationship between the standard deviation of unit current sources, the bits of resolution, the INL/DNL, and the soft yield of DAC arrays. It is shown that these formulas are very effective for optimizing the DAC segmentation so as to achieve high performance and high yield with minimal area and power consumption. To overcome random mismatch effects without any trimming, the current source array of a high-accuracy DAC is usually rather large, causing the gradient errors in these arrays to become significant. How gradient errors affect the DAC linearity and how to compensate for them through switching sequence optimization is analyzed in the second part of this dissertation. To overcome technology barriers, relax the requirements on layout and reduce the sensitivities of DACs to process, temperature and aging, calibration is emerging as an attractive solution for the next-generation high-performance DACs, especially as process feature size keeps shrinking and supply voltage is reduced correspondingly. A new foreground calibration technique suitable for low-voltage environment is presented in the third part of this dissertation. It can effectively compensate for current source mismatches, and achieve high linearity with small die size and low power consumption. The dynamic performance of the DAC is also improved due to the dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit prototype was designed and fabricated in a 0.13u digital CMOS process. It is the first 14-bit CMOS DAC ever reported that operates with a single 1.5V power supply, occupies an active area less than 0.1mm2, and requires only 16.7mW at 100MHz sampling rate, but still maintains state-of-art linearity and speed

Dynamic calibration of current-steering DAC

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values

Low power GaAs digital and analog functionalities for microwave signal conditioning in AESA systems

A MMIC demonstrator for RF phase and amplitude control with on board 18-bit serial to parallel conversion (Multi-Functional Chip) is presented. Thanks to an alternative digital building block topology, the DC power consumption of the digital serial to parallel converter is noteworthy: less than 43 mW (2 mW/bit). The main RF performances are 0° - 360° phase coverage and 0 dB - 31.5 dB attenuation setting, in the 7.6 GHz - 9.1 GHz operating bandwidth. The circuit, whose area is 6 mm2, is realised in an industrial and commercially available GaAs technology. This component can be used in active electronically scanned arrays for beam steering

Switched-Capacitor Voltage Doubler Design Using 0.5 μm Technology

While integrated circuit (IC) power management has been an eternal topic for chip designers, inductor based DC-DC converters have been dominant in the field for years. However, because of the natures of inductors: large electro-magnetic interference, high coupling noise, and difficult silicon fabrication process, they are not favorable to on-chip solutions. Switched-capacitor (SC) DC-DC converters, which adopt capacitors for their energy storage components, have become increasingly popular among both the academia and the industry, because, apparently, they avoid the drawbacks of the inductor counterparts, and can be directly implemented on-chip without additional fabrication process. In this paper, we will investigate one of the most famous SC voltage doubler topologies, which is known as Favrat Cell . By designing a chip, which converts 1.5 V voltage input to 2.5 V voltage output at 1 mA current load, we will walk through the details of a SC DC-DC converter design, including the switch cell, timing system, regulation loop and efficiency analysis. The design uses two 200 pF pumping capacitors and a 400 pF output capacitor in On-Semi half-micron technology. Four-way interleaved phase structure is adopted to reduce the output voltage ripple. The gate-drive strategy of the switches has been improved to further reduce the reverse current injections during transitions. A new high-ratio voltage booster topology based on the cross-coupled topology has been introduced and will be discussed in comparison with the Dickson charge pump topology

High-speed Design Of High-resolution Dacs

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu çalışmada, yüksek çözünürlüklü akım yönlendirmeli sayısal-analog dönüştürücülerin (SAD) hızlı tasarımını sağlayan yöntemler incelenmekte ve yeni yaklaşımlar önerilmektedir. Veri dönüştürücüler analog ve sayısal dünyalar arasında bir köprü oluşturdukları için hızlı ve verimli bir şekilde gerçekleştirilmeleri yüksek derecede arzu edilmektedir. Yüksek hızlı (birkaç 100MHz) ve yüksek çözünürlüklü (10 bitten fazla) SAD için artan rağbet, akım yönlendirmeli SADların kullanımını zorunlu kılmaktadır. Yüksek performanslı akım yönlendirmeli SADların tasarımında ve gerçekleştirmesinde kesimleme (segmentation) yöntemi kullanılmaktadır. Bu yöntem, yüksek hız ve yüksek çözünürlük gerektiren uygulamaların çoğunda avantajlı olmasına rağmen uzun süreli tasarım zamanı, karmaşıklık ve yüksek maliyet yüzünden değer kaybetmektedir. Böylece, bazı uygulamalar için zaman ve maliyet açısından bu yöntemin kullanılması hızlı ve verimli olmayabilir. Bu problemlerin üstesinden gelmek için yüksek çözünürlüklü SADların yüksek hızlı tasarımını sağlayan hızlı ve verimli yöntemler dikkate alınmaktadır. Uygun bir tasarım yöntemi ve yeni bir yapı önerilmektedir. Akım yönlendirmeli SADlar gibi karmaşık karma yapılı sistemlerin tasarımı için davranışsal modelin oluşturulması zorunlu olmaktadır. Bu amaçla gerçekleştirilen modellerin çoğu sistemin davranışı hakkında istenilen eksiksiz manzarayı vermemektedir. Bu yüzden, transistor seviyesindeki tasarıma geçmeden önce, tasarımı hızlandırabilen ve sistemin davranışını doğru bir şekilde yansıtabilen modeller geliştirilmektedir. SIMULINK® kullanılarak bir davranışsal model kurulmakta ve modelin performansı benzetimlerle sınanmaktadır. Sonuç olarak, uygulanan yöntemin verimliliğini ve davranışsal modelin doğruluğunu sınamak için 0.35µm CMOS proses teknolojisi için tasarlanan bir 12 bitlik melez akım yönlendirmeli SAD kullanılmaktadır. Yapı bloklarında yapılan iyileştirmeler ve kullanılan farklı yöntemler, gerçekleştirilen SAD’ın serimindeki ilgili kısımlarda yer almaktadırlar. CADENCE Geleneksel Tümleşik Devre Tasarım Araçları kullanılarak serim sonrası benzetimleri yapılmakta ve SAD’ın performans karakteristikleri incelenmektedir.In this thesis, different problems related to the design speed-up of high-resolution current-steering digital-to-analog converters (DAC) are addressed and novel solutions are proposed. Since data converters form the bridge between the analog and digital world their efficient implementation is highly desirable. The increase in demand for high-speed (several 100MHz) and high-resolution (higher than 10-bit) DAC, forces the use of current-steering DACs. Segmentation method is used for the design and the implementation of high performance current-steering DACs. Although this methodology is advantageous in most of the applications requiring high-speed and high-resolution, it suffers from the prolonged design time, complexity and high cost. Thus, the use of this methodology for some applications is not efficient concerning the time and the cost. To overcome these problems efficient methodologies for the high-speed design of high-resolution DACs are considered. A proper design methodology and a novel architecture are introduced. Behavioral modeling is necessary for the design of complex mixed-mode systems like current-steering DACs. Most of the models constructed can not give a complete view of the system’s behavior. For this reason, models that speed up the design and reflect accurately the behavior of the system prior to transistor level implementation are developed. A SIMULINK® based behavioral model is developed and verified through simulations. To conclude, the efficiency of the applied methodology and the accuracy of the behavioral model are validated through the implementation of a 12-bit hybrid current-steering DAC in a 0.35µm CMOS process technology. The improvements in the building blocks and the different approaches used are reflected in the respective parts of the layout of the implemented DAC. Post-layout simulations are obtained using CADENCE Custom IC Design Tools and the performance metrics of the DAC are investigated.DoktoraPh