The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values
