On Entropy and Bit Patterns of Ring Oscillator Jitter

Thermal jitter (phase noise) from a free-running ring oscillator is a common, easily implementable physical randomness source in True Random Number Generators (TRNGs). We show how to evaluate entropy, autocorrelation, and bit pattern distributions of ring oscillator noise sources, even with low jitter levels or some bias. Entropy justification is required in NIST 800-90B and AIS-31 testing and for applications such as the RISC-V entropy source extension. Our numerical evaluation algorithms outperform Monte Carlo simulations in speed and accuracy. We also propose a new lower bound estimation formula for the entropy of ring oscillator sources which applies more generally than previous ones.Comment: 6 page

D2.1 - Report on Selected TRNG and PUF Principles

This report represents the final version of Deliverable 2.1 of the HECTOR work package WP2. It is a result of discussions and work on Task 2.1 of all HECTOR partners involved in WP2. The aim of the Deliverable 2.1 is to select principles of random number generators (RNGs) and physical unclonable functions (PUFs) that fulfill strict technology, design and security criteria. For example, the selected RNGs must be suitable for implementation in logic devices according to the German AIS20/31 standard. Correspondingly, the selected PUFs must be suitable for applying similar security approach. A standard PUF evaluation approach does not exist, yet, but it should be proposed in the framework of the project. Selected RNGs and PUFs should be then thoroughly evaluated from the point of view of security and the most suitable principles should be implemented in logic devices, such as Field Programmable Logic Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) during the next phases of the project

Hot-carrier reliability assessment in CMOS digital integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references.by Wenjie Jiang.Ph.D

DART: Dependable VLSI Test Architecture and Its Implementation

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.2012 IEEE International Test Conference, 5-8 November 2012, Anaheim, CA, US

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Kytketyt MEMS-resonaattoriverkot

Micromechanical resonance frequencies are in a standard manner a few tens of MHz and can even cover the requency range up to a few GHz. When using high quality material such as quartz of silicon, also internal losses are very low. By physical coupling of resonators into a network, one can realize various mechanical signal processing, filtering or for example neural network type behavior. Since coupling between resonators are realized by some kind of bridge, which can be either rather linear or alternatively intentionally very nonlinear, the overall behavior of the whole network is very complex. Of general interest are effects that originate from multiple inputs and outputs and which could lead to a rather unexpected spectral or transient behavior of the signals, which can be found by computer modelling.Mikromekaaniset resonanssitaajuudet ovat tyypillisesti muutamia kymmeniä megahertsejä mutta voivat kattaa taajuuskaistan aina muutamiin gigahertseihin asti. Käytettäessä korkealaatuisia materiaaleja kuten kvartsia tai piitä myös signaalin häviöt ovat erittäin pieniä. Kytkemällä resonaattoreita fyysiseksi verkoksi voidaan mekaanisilla rakenteilla suorittaa signaalinkäsittelyä, realisoida suodattimia ja jopa neuroverkkoja. Koska yksittäisten resonaattorien välinen kytkentä on jonkinlainen silta, joka voi olla joko melko lineaarinen tai vaihtoehtoisesti tarkoituksellisesti erittäin epälineaarinen, on koko verkon käyttäytyminen erittäin monimutkaista. Yleisesti kiinnostavia ovat useista sisäänmenoista ja ulostuloista johtuvat ilmiöt, jotka voivat johtaa signaalien spektrin tai transienttivasteen melko odottamattomaan tai epäintuitiiviseen käyttäytymiseen, jonka voi löytää ja tulkita tietokonesimulaatioilla

Large Scale Stochastic Dynamics

Equilibrium statistical mechanics studies random fields distributed according to a Gibbs probability measure. Such random fields can be equipped with a stochastic dynamics given by a Markov process with the correspondingly high-dimensional state space. One particular case are stochastic partial differential equations suitably regularized. Another common version is to consider the evolution of random fields taking only values 0 or 1. The workshop was concerned with an understanding of qualitative properties of such high-dimensional Markov processes. Of particular interest are nonreversible dynamics for which the stationary measures are determined only through the dynamics and not given a priori (as would be the case for reversible dynamics). As a general observation, properties on a large scale do not depend on the precise details of the local updating rules. Such kind of universality was a guiding theme of our workshop

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constraints (energy consumption, time-to-market). Moreover, the rise of temperature in the die for MPSoCs can seriously affect their final performance and reliability. In this paper, we present a new hardware-software emulation framework that allows designers a complete exploration of the thermal behavior of final MPSoC designs early in the design flow. The proposed framework uses FPGA emulation as the key element to model the hardware components of the considered MPSoC platform at multi-megahertz speeds. It automatically extracts detailed system statistics that are used as input to our software thermal library running in a host computer. This library calculates at run-time the temperature of on-chip components, based on the collected statistics from the emulated system and the final floorplan of the MPSoC. This enables fast testing of various thermal management techniques. Our results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulator

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Hot-carrier reliability evaluation for CMOS devices and circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 138-139).by Vei-Han Chan.Ph.D