Efficient optimization of the integrity behavior of analog nonlinear devices using surrogate models

A novel technique to analyze and optimize the integrity behavior of nonlinear analog devices in the presence of noise is proposed. The technique leverages surrogate models, as such reducing the simulation time, avoiding time-consuming and expensive measurements after tape-out and hiding the original netlist of the circuit, while maintaining high accuracy. Easy integration of the surrogates into a circuit simulator together with pertinent subcircuits representing, e. g., board and package, allows mimicking the integrity behavior of a complete setup while still being in the design phase. In this contribution, the method is applied to a case study, being a voltage regulator designed for automotive applications

A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression

This paper introduces a probabilistic machine learning framework for the uncertainty quantification (UQ) of electronic circuits based on Gaussian process regression (GPR). As opposed to classical surrogate modeling techniques, GPR inherently provides information on the model uncertainty. The main contribution of this work is twofold. First, it describes how, in an UQ scenario, the model uncertainty can be combined with the uncertainty of the input design parameters to provide confidence bounds for the statistical estimates of the system outputs, such as moments and probability distributions. These confidence bounds allows assessing the accuracy of the predicted statistics. Second, in order to deal with dynamic multi-output systems, principal component analysis (PCA) is effectively employed to compress the time-dependent output variables into a smaller set of components, for which the training of individual GPR models becomes feasible. The uncertainty on the principal components is then propagated back to the original output variables. Several application examples, ranging from a trivial RLC circuit to real-life designs, are used to illustrate and validate the advocated approach

Statistical Performance Modeling of SRAMs

Yield analysis is a critical step in memory designs considering a variety of performance constraints. Traditional circuit level Monte-Carlo simulations for yield estimation of Static Random Access Memory (SRAM) cell is quite time consuming due to their characteristic of low failure rate, while statistical method of yield sensitivity analysis is meaningful for its high efficiency. This thesis proposes a novel statistical model to conduct yield sensitivity prediction on SRAM cells at the simulation level, which excels regular circuit simulations in a significant runtime speedup. Based on the theory of Kriging method that is widely used in geostatistics, we develop a series of statistical model building and updating strategies to obtain satisfactory accuracy and efficiency in SRAM yield sensitivity analysis. Generally, this model applies to the yield and sensitivity evaluation with varying design parameters, under the constraints of most SRAM performance metric. Moreover, it is potentially suitable for any designated distribution of the process variation regardless of the sampling method

An efficient analog circuit sizing method based on machine learning assisted global optimization

Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog IC design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: (1) The prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent. (2) The machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called Efficient Surrogate Model-assisted Sizing Method for High-performance Analog Building Blocks (ESSAB), is proposed in this paper to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performances. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB

Yield Analysis and Optimization of Microwave Devices and Antennas using Non-Linear Partial-Least-Squares Based Polynomial Chaos Expansion

Electrical and Electronic Engineerin

Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition

Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient ANOVA-based stochastic circuit/MEMS simulator to extract efficiently the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is simulated efficiently by our simulator at the cost of only 10 minutes in MATLAB on a regular personal computer.Comment: 14 pages (IEEE double column), 11 figure, accepted by IEEE Trans CAD of Integrated Circuits and System