Sistemas de teste automáticos para transceivers NG-PON2

Optical communications have had a fundamental role in conecting people worldwide. More than ever, there has been an incessant necessity to turn technology more ubiquitous With recent advancements in optical technology, it has become possible to keep up with the demand for higher transmission rates in upstream or downstream, higher bandwidth e still guaranteeing Quality of Service (QoS) among inumerous users This emerging necessity has taken telecommunication companies to inovate in the area of development regarding optical equipment and also dealing with the referred necessities. For this to happen, good quality control, calibration e testing of produced parts is of paramount importance. The work cut out for this dissertation is focused on the improvement and addition of funtionalities to a test-board designed to perform measurements of BER levels, calibration and maintenance of parts according to the newest optical standard(New Gigabit Passive Optical Network 2 (NGPON2)) that operates in maximum rates of 10Gb/s per channel. In the rst part of this work, emphasis is given to the development of a slave Inter Integrated Circuit (I2C) module that ensures connection between the test board and the user, supplying BER values measured through a block dedicated to measure BER levels. Later the same module will allow to access all micro-controlers of the test-board, ensuring calibration functions. On a second part, a characterization of different transceivers of different Field Programmable Gate Array (FPGA)s is performed, consisting of an eye diagram analysis of the transceivers and if possible, to test 10Gb/s continuous mode through BER curves assessing their response. Finally, a comparison is made between all transceivers, the obtained response along with all the respective results, will contribute to the source project of the automatic test board developed at PICadvanced with the intent on evaluating 10 Gigabit Small Form Factor Pluggables (XFP) production.As comunicações têm vindo a ter um papel fundamental em interligar todas as pessoas do mundo. Mais do que nunca, tem havido uma incessante necessidade de tornar a tecnologia mais ubíqua. Com o recente avanço e desenvolvimento da tecnologia Optica, tem sido possível acompanhar a demanda por altas taxas de transmissão em upstream ou downstream, maior largura de banda e ainda garantir Quality of Service (QoS) entre ínumeros utilizadores, etc. . . Esta necessidade emergente tem levado empresas de telecomunicações a inovar na área de desenvolvimento de equipamento óptico e por consequente, comaltar as necessidades referidas. Para isto acontecer tem de haver um bom controlo, calibração e teste de peças produzidas. O trabalho desta dissertação dedica-se ao melhoramento e acrescento de funcionalidades a uma placa de testes desenhada para desempenhar medições de níveis de Bit Error Ratio (BER), calibração e manutenção de peças para o novo standard óptico (New Gigabit Passive Optical Network 2 (NGPON2)) que recorre ao uso de taxas máximas de transmissão de 10Gb/s por canal Na primeira parte do trabalho é dado foco ao desenvolvimento de um módulo escravo Inter Integrated Circuit (I2C) que visa estabelecer o contacto entre a placa de calibração e o utilizador fornecendo os valores de BER medidos através de um bloco dedicado a medir o nível de BER. Mais tarde este módulo servirá para poder aceder aos micro-circuitos da placa de testes podendo realizar funções de calibração. Numa segunda parte, é realizada uma caracterização de diferentes transceivers de diferentes Field Programmable Gate Array (FPGA)s, a caracterização consiste numa análise do diagram de olho de transceivers e ainda sendo possível, testar o modo contínuo nas mesmas, através curvas de BER para avaliar a sua resposta. Por fim, é feita uma comparação entre os mesmos transceivers, além de que todos os resultados obtidos irão contribuir para a o projecto fonte da placa de testes automatizada desenvolvida pela PICadvanced com o intuito de avaliar a produção de 10 Gigabit Small Form Factor Pluggables (XFP).Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Design and Implementation of High-Speed Data Transmission on Multi-Gigabit Transceivers in Spartan 6 FPGA

This paper gives the design of link where the parallel digital data are transmitted serially at the rate of 3.125Gbps on the Spartan 6 evaluation board. The implemented design is to test Aurora 8b/10b protocol in order to transfer 16-bit parallel data serially over the fiber optic cable in full duplex mode. The 16-bit Parallel data are transmitted and received by the Serialized/De-serialized (SERDES) using Multi-Giga bit transceiver (MGT) at the clock rate of 156.25MHz.Aurora protocol converts the parallel data to serial and serial to parallel. The proposed design is simulated in Xilinx 14.2 and implemented on Spartan 6 FPGA. The serial data are transmitted at the rate of 3.125Gbps over the fiber optic link. DOI: 10.17762/ijritcc2321-8169.15054

A Fully Bidirectional Optical Network With Latency Monitoring Capability for the Distribution of Timing-Trigger and Control Signals in High-Energy Physics Experiments

The present paper discusses recent advances on a Passive Optical Network inspired Timing-Trigger and Control scheme for the future upgrade of the TTC system installed in the LHC experiments' and more specifically the currently known as TTCex to TTCrx link. The timing PON is implemented with commercially available FPGAs and 1-Gigabit Ethernet PON transceivers and provides a fixed latency gigabit downlink that can carry level-1 trigger accept decisions and commands as well as an upstream link for feedback from the front-end electronics

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed

Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links

The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results

A LVDS Serial AER Link

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0

Sistemas de calibração automático para transceivers NG-PON2

The current society is increasingly dependent on communication services, requiring better and faster connections, predicting in a near future connections in the order of hundreds of Gbit/s. During the data transmissions, the increase of speed reflects an increase of the error ratio due to factors such as noise, reductions of signal or jitter, which for low speed these were not emphasized so much. This project involves the development of a BER test system for both continuous and Burst mode of the transmission, demonstrating the viability of communication over the next-generation technology, NG-PON2, which uses high transmission rates (10 Gbit/s). For this purpose, an FPGA architecture was implemented that allows for long distances in the optical network, high transmission rates. This choice reflects a more economical alternative in relation to commercial equipment and has several advantages, such as the flexibility to reprogram and prepare the architecture according to the needs of the user. To achieve the proposed requirements, the project was divided into three parts. In the first part an architecture was developed that allows to obtain the error rate during a continuous mode transmission. In order to obtain the real-time viability of the communication referred and to have control over the system, an interface was developed between the computer and the FPGA to change certain characteristics of the communication channel. This is the second part of the project. The last part of the project has an architecture similar to the previous one, that is, instead of the transmission to be done in continuous mode, it is performed in mode Burst, being this the requirement with more interest to the technology NG-PON2. Finally, proof of concept was performed through an optical network provided by the company PICadvanced that allowed the validation of the different parts of the project. These validations will allow the development of new modules that will later contribute to the main project that is under development in the company PICadvanced, which aims at the construction of an automatic calibration board for the XFP transceivers.A sociedade atual depende cada vez mais dos serviços de comunicação, exigindo melhores ligações e mais rápidas, prevendo-se num futuro próximo a necessidade de ligações na ordem das centenas de Gbit/s. O aumento dos ritmos de transmissão refletem um aumento no que se refere à taxa de erro (BER), uma vez que o impacto associado a fatores como ruı́do ou interferência entre sı́mbolos, é maior do que para baixos ritmos. Este trabalho foca-se no desenvolvimento de um sistema de teste BER, tanto para uma transmissão contı́nua como para transmissão em rajadas, que demonstre a viabilidade da comunicação sobre a tecnologia da próxima geração, Next Generation Passive Optical Network 2 (NG-PON2), que utiliza débitos de transmissão elevados (10 Gbit/s). Para este efeito foi implementado uma arquitetura em Field-programmable gate array (FPGA) que possibilita para longas distâncias na rede ótica, elevados ritmos de transmissão. Esta escolha reflete uma alterativa mais económica em relação aos equipamentos comerciais e apresenta vantagens tais como a flexibilidade de reprogramar e preparar a arquitetura de acordo com as necessidades do utilizador. Para cumprir os requisitos propostos o projeto dividiu-se em três partes. Numa primeira parte do projeto desenvolveu-se uma arquitetura que permite adquirir a taxa de erros durante uma transmissão contı́nua. Com o intuito de analisar a viabilidade em tempo real da comunicação em questão, bem com o utilizador ter controlo sobre o sistema, alterando certas caracterı́sticas do canal de comunicação, desenvolveu-se numa segunda parte do projeto uma interface entre o computador e a FPGA. Numa última parte do projeto desenvolveu-se uma arquitetura semelhante à anterior, na qual se permite igualmente adquirir a taxa de erros com transmissão em rajadas (Burst), sendo este um dos requisitos de maior interesse na tecnologia NG-PON2. Por fim, a prova de conceito foi realizada através de uma rede ótica disponibilizada pela empresa PICadvanced, que permitiu a validação das diversas partes do projeto. Estas validações vão permitir a conceção de novos módulos que posteriormente vão contribuir para o projeto fonte que está em desenvolvimento na empresa PICadvanced, que visa a implementação de uma placa de calibração automatizada para os transceptores 10 Gigabit Small Form Factor Pluggables (XFP).Mestrado em Engenharia Eletrónica e Telecomunicaçõe